SYSLAB blog

　[RX600-RX630] .fvectors|0|0||1|0xFFFFFFA0|0|1|0|.fvectors|All-files|<<FEND>>|<<CEND>>|<<GEND>>|.text|0|0||1|0xFFFC0000|0|0|0|.text|All-files|<<FEND>>|0|.text.*|All-files|<<FEND>>|0|P|All-files|<<FEND>>|1|etext|<<FEND>>|<<CEND>>|<<GEND>>|.rvectors|0|0||0||0|1|1|_rvectors_start|<<FEND>>|0|.rvectors|All-files|<<FEND>>|1|_rvectors_end|<<FEND>>|<<CEND>>|<<GEND>>|.init|0|0||0||0|0|0|.init|All-files|<<FEND>>|1|__preinit_array_start|<<FEND>>|0|.preinit_array|All-files|<<FEND>>|1|__preinit_array_end|<<FEND>>|1|__init_array_start____=____(.____+____3)____&____~____3|<<FEND>>|0|.init_array|All-files|<<FEND>>|0|SORT(.init_array.*)|All-files|<<FEND>>|1|__init_array_end|<<FEND>>|1|__fini_array_start|<<FEND>>|0|.fini_array|All-files|<<FEND>>|0|SORT(.fini_array.*)|All-files|<<FEND>>|1|__fini_array_end|<<FEND>>|<<CEND>>|<<GEND>>|.fini|0|0||0||0|0|0|.fini|All-files|<<FEND>>|<<CEND>>|<<GEND>>|.got|0|0||0||0|0|0|.got|All-files|<<FEND>>|0|.got.plt|All-files|<<FEND>>|<<CEND>>|<<GEND>>|.rodata|0|0||0||0|0|0|.rodata|All-files|<<FEND>>|0|.rodata.*|All-files|<<FEND>>|0|C_1|All-files|<<FEND>>|0|C_2|All-files|<<FEND>>|0|C|All-files|<<FEND>>|1|_erodata|<<FEND>>|<<CEND>>|<<GEND>>|.eh_frame_hdr|0|0||0||0|0|0|.eh_frame_hdr|All-files|<<FEND>>|<<CEND>>|<<GEND>>|.eh_frame|0|0||0||0|0|0|.eh_frame|All-files|<<FEND>>|<<CEND>>|<<GEND>>|.jcr|0|0||0||0|0|0|.jcr|All-files|<<FEND>>|<<CEND>>|<<GEND>>|.tors|0|0||0||0|0|1|__CTOR_LIST__|<<FEND>>|1|___ctors|<<FEND>>|0|.ctors|All-files|<<FEND>>|1|___ctors_end|<<FEND>>|1|__CTOR_END__|<<FEND>>|1|__DTOR_LIST__|<<FEND>>|1|___dtors|<<FEND>>|0|.dtors|All-files|<<FEND>>|1|___dtors_end|<<FEND>>|1|__DTOR_END__|<<FEND>>|1|_mdata|<<FEND>>|<<CEND>>|<<GEND>>|.istack|0|0||1|0x00001808|0|0|1|_istack|<<FEND>>|<<CEND>>|<<GEND>>|.ustack|0|0||1|0x00001708|0|0|1|_ustack|<<FEND>>|<<CEND>>|<<GEND>>|.data|0|2|_mdata|1|0x00001000|0|0|1|_data|<<FEND>>|0|.data|All-files|<<FEND>>|0|.data.*|All-files|<<FEND>>|0|D|All-files|<<FEND>>|0|D_1|All-files|<<FEND>>|0|D_2|All-files|<<FEND>>|1|_edata|<<FEND>>|<<CEND>>|<<GEND>>|.gcc_exc|0|0||0||0|0|0|.gcc_exc|All-files|<<FEND>>|<<CEND>>|<<GEND>>|.bss|0|0||0||0|0|1|_bss|<<FEND>>|0|.bss|All-files|<<FEND>>|0|.bss.*|All-files|<<FEND>>|0|COMMON|All-files|<<FEND>>|0|B|All-files|<<FEND>>|0|B_1|All-files|<<FEND>>|0|B_2|All-files|<<FEND>>|1|_ebss|<<FEND>>|1|_end|<<FEND>>|<<CEND>>|<<GEND>>

　;2011.04 ; [Files] 1=resetprg\rx630.asm 2=1 3=DBsct\rx.c 4=IntPRG\rx630.c 5=vecttbl\rx630.c 6=lowlvl\rx.src 7=lowsrc\rx.c 8=sbrk\rx.c 9=iodefine\rx630.h 10=vect\rx630.h 11=hwsetup\rx630.c 12=lowsrc\rx.h 13=sbrk\rx.h 14=0 15=1 16=1 17=Common\Main.c 18=Common\typedefine.h Asm 11=hwsetup\rx.src Demo 17=Common\Sort.c [CPU Type Data] I/O Stream=20 Heap Size=0x400 Hw Setup Function=HardwareSetup User Stack Size=0x300 Interrupt Stack Size=0x100 Summary 0= Summary 1= Summary 2=\n Summary 3=Program start 0xFFE00000. Summary 4=RAM start 0x00000400. [Section] Reset Section= Reset Address= Vector Section=.vectors Vector Address=FFFFFFD0 ResetPRG Section=PResetPRG ResetPRG Address=FFFF8000 Program Section=.text,.rodata Program Address=FFE00000 B Section=.data,.bss B Address=00000400 Stack Section=.stack Stack Address=00100000 [C++ Section] Reset Section= Reset Address= Vector Section=.vectors Vector Address=FFFFFFD0 ResetPRG Section=PResetPRG ResetPRG Address=FFFF8000 Program Section=.text,.rodata Program Address=FFE00000 B Section=.data,.bss B Address=00000400 Stack Section=.stack Stack Address=00100000 [Option] Compiler= Assembler= Optimizer= Converter= Librarian=

　//2005.01 #include "iodefine.h" #ifdef __cplusplus extern "C" { #endif extern void HardwareSetup(void); #ifdef __cplusplus } #endif void HardwareSetup(void) { /* SCI.SMR.BYTE = 0; SCI.SMR.BIT.CA = 1; SCI.SMR.BIT.CHR = 1; SCI.SMR.BIT.OE = 1; SCI.SMR.BIT.STOP = 1; SCI.SMR.BIT.MP = 1; SCI.SMR.BIT.CKS = 3; SCI.BRR = 0; SCI.SCR.BYTE = 0; SCI.SCR.BIT.TIE = 1; SCI.SCR.BIT.RIE = 1; SCI.SCR.BIT.TE = 1; SCI.SCR.BIT.RE = 1; SCI.SCR.BIT.MPIE = 1; SCI.SCR.BIT.TEIE = 1; SCI.SCR.BIT.CKE = 3; SCI.TDR = 0; SCI.SSR.BYTE = 0; SCI.SSR.BIT.TDRE = 1; SCI.SSR.BIT.RDRF = 1; SCI.SSR.BIT.ORER = 1; SCI.SSR.BIT.FER = 1; SCI.SSR.BIT.PER = 1; SCI.SSR.BIT.TEND = 1; SCI.SSR.BIT.MPB = 1; SCI.SSR.BIT.MPBT = 1; SCI.RDR = 0; */ }

　/***********************************************************************/ /* */ /* FILE :interrupt_handlers.c */ /* DATE :Thu, Jan 20, 2011 */ /* DESCRIPTION :Interrupt Handler */ /* CPU TYPE :RX630 */ /* */ /* This file is generated by KPIT GNU Project Generator. */ /* */ /***********************************************************************/ #include "interrupt_handlers.h" // Exception(Supervisor Instruction) void INT_Excep_SuperVisorInst(void){/* brk(); */} // Exception(Undefined Instruction) void INT_Excep_UndefinedInst(void){/* brk(); */} // Exception(Floating Point) void INT_Excep_FloatingPoint(void){/* brk(); */} // NMI void INT_NonMaskableInterrupt(void){/* brk(); */} // Dummy void Dummy(void){/* brk(); */} // BRK void INT_Excep_BRK(void){ /*wait(); */} //;0x0000 Reserved //;0x0004 Reserved //;0x0008 Reserved //;0x000C Reserved //;0x0010 Reserved //;0x0014 Reserved //;0x0018 Reserved //;0x001C Reserved //;0x0020 Reserved //;0x0024 Reserved //;0x0028 Reserved //;0x002C Reserved //;0x0030 Reserved //;0x0034 Reserved //;0x0038 Reserved //;0x003C Reserved //;0x0040 BUSERR void INT_Excep_BUSERR(void){ } //;0x0044 Reserved //;0x0048 Reserved //;0x004C Reserved //;0x0050 Reserved //;0x0054 FCUERR void INT_Excep_FCU_FCUERR(void){ } //;0x0058 Reserved //;0x005C FRDYI void INT_Excep_FCU_FRDYI(void){ } //;0x0060 Reserved //;0x0064 Reserved //;0x0068 Reserved //;0x006C ICU_SWINT void INT_Excep_ICU_SWINT(void){ } //;0x0070 CMTU0_CMI0 void INT_Excep_CMTU0_CMI0(void){ } //;0x0074 CMTU0_CMI1 void INT_Excep_CMTU0_CMI1(void){ } //;0x0078 CMTU1_CMI2 void INT_Excep_CMTU1_CMI2(void){ } //;0x007C CMTU1_CMI3 void INT_Excep_CMTU1_CMI3(void){ } //;0x0080 Reserved //;0x0084 USB0_D0FIFO0 void INT_Excep_USB0_D0FIFO0(void){ } //;0x0088 USB0_D1FIFO0 void INT_Excep_USB0_D1FIFO0(void){ } //;0x008C USB0_USBI0 void INT_Excep_USB0_USBI0(void){ } //;0x0090 Reserved //;0x0094 Reserved //;0x0098 Reserved //;0x009C RSPI0_SPRI0 void INT_Excep_RSPI0_SPRI0(void){ } //;0x00A0 RSPI0_SPTI0 void INT_Excep_RSPI0_SPTI0(void){ } //;0x00A4 RSPI0_SPII0 void INT_Excep_RSPI0_SPII0(void){ } //;0x00A8 RSPI1_SPRI1 void INT_Excep_RSPI1_SPRI1(void){ } //;0x00AC RSPI1_SPTI1 void INT_Excep_RSPI1_SPTI1(void){ } //;0x00B0 RSPI1_SPII1 void INT_Excep_RSPI1_SPII1(void){ } //;0x00B4 RSPI2_SPRI2 void INT_Excep_RSPI2_SPRI2(void){ } //;0x00B8 RSPI2_SPTI2 void INT_Excep_RSPI2_SPTI2(void){ } //;0x00BC RSPI2_SPII2 void INT_Excep_RSPI2_SPII2(void){ } //;0x00C0 CAN0_RXF0 void INT_Excep_CAN0_RXF0(void){ } //;0x00C4 CAN0_TXF0 void INT_Excep_CAN0_TXF0(void){ } //;0x00C8 CAN0_RXM0 void INT_Excep_CAN0_RXM0(void){ } //;0x00CC CAN0_TXM0 void INT_Excep_CAN0_TXM0(void){ } //;0x00D0 CAN1_RXF1 void INT_Excep_CAN1_RXF1(void){ } //;0x00D4 CAN1_TXF1 void INT_Excep_CAN1_TXF1(void){ } //;0x00D8 CAN1_RXM1 void INT_Excep_CAN1_RXM1(void){ } //;0x00DC CAN1_TXM1 void INT_Excep_CAN1_TXM1(void){ } //;0x00E0 CAN2_RXF2 void INT_Excep_CAN2_RXF2(void){ } //;0x00E4 CAN2_TXF2 void INT_Excep_CAN2_TXF2(void){ } //;0x00E8 CAN2_RXM2 void INT_Excep_CAN2_RXM2(void){ } //;0x00EC CAN2_TXM2 void INT_Excep_CAN2_TXM2(void){ } //;0x00F0 Reserved //;0x00F4 Reserved //;0x00F8 RTC_COUNTUP void INT_Excep_RTC_COUNTUP(void){ } //;0x00FC Reserved //;0x0100 IRQ0 void INT_Excep_IRQ0(void){ } //;0x0104 IRQ1 void INT_Excep_IRQ1(void){ } //;0x0108 IRQ2 void INT_Excep_IRQ2(void){ } //;0x010C IRQ3 void INT_Excep_IRQ3(void){ } //;0x0110 IRQ4 void INT_Excep_IRQ4(void){ } //;0x0114 IRQ5 void INT_Excep_IRQ5(void){ } //;0x0118 IRQ6 void INT_Excep_IRQ6(void){ } //;0x011C IRQ7 void INT_Excep_IRQ7(void){ } //;0x0120 IRQ8 void INT_Excep_IRQ8(void){ } //;0x0124 IRQ9 void INT_Excep_IRQ9(void){ } //;0x0128 IRQ10 void INT_Excep_IRQ10(void){ } //;0x012C IRQ11 void INT_Excep_IRQ11(void){ } //;0x0130 IRQ12 void INT_Excep_IRQ12(void){ } //;0x0134 IRQ13 void INT_Excep_IRQ13(void){ } //;0x0138 IRQ14 void INT_Excep_IRQ14(void){ } //;0x013C IRQ15 void INT_Excep_IRQ15(void){ } //;0x0140 Reserved //;0x0144 Reserved //;0x0148 Reserved //;0x014C Reserved //;0x0150 Reserved //;0x0154 Reserved //;0x0158 Reserved //;0x015C Reserved //;0x0160 Reserved //;0x0164 Reserved //;0x0168 USB_USBR0 void INT_Excep_USB_USBR0(void){ } //;0x016C Reserved //;0x0170 RTC_ALARM void INT_Excep_RTC_ALARM(void){ } //;0x0174 RTC_PRD void INT_Excep_RTC_PRD(void){ } //;0x0178 Reserved //;0x017C Reserved //;0x0180 Reserved //;0x0184 Reserved //;0x0188 AD0_ADI0 void INT_Excep_AD0_ADI0(void){ } //;0x018C Reserved //;0x0190 Reserved //;0x0194 Reserved //;0x0198 S12AD0_S12ADI0 void INT_Excep_S12AD0_S12ADI0(void){ } //;0x019C Reserved //;0x01A0 Reserved //;0x01A4 Reserved //;0x01A8 ICU_GE0 void INT_Excep_ICU_GE0(void){ } //;0x01AC ICU_GE1 void INT_Excep_ICU_GE1(void){ } //;0x01B0 ICU_GE2 void INT_Excep_ICU_GE2(void){ } //;0x01B4 ICU_GE3 void INT_Excep_ICU_GE3(void){ } //;0x01B8 ICU_GE4 void INT_Excep_ICU_GE4(void){ } //;0x01BC ICU_GE5 void INT_Excep_ICU_GE5(void){ } //;0x01C0 ICU_GE6 void INT_Excep_ICU_GE6(void){ } //;0x01C4 Reserved //;0x01C8 ICU_GL0 void INT_Excep_ICU_GL0(void){ } //;0x01CC Reserved //;0x01D0 Reserved //;0x01D4 Reserved //;0x01D8 Reserved //;0x01DC Reserved //;0x01E0 Reserved //;0x01E4 Reserved //;0x01E8 SCIX_SCIX0 void INT_Excep_SCIX_SCIX0(void){ } //;0x01EC SCIX_SCIX1 void INT_Excep_SCIX_SCIX1(void){ } //;0x01F0 SCIX_SCIX2 void INT_Excep_SCIX_SCIX2(void){ } //;0x01F4 SCIX_SCIX3 void INT_Excep_SCIX_SCIX3(void){ } //;0x01F8 TPU0_TGI0A void INT_Excep_TPU0_TGI0A(void){ } //;0x01FC TPU0_TGI0B void INT_Excep_TPU0_TGI0B(void){ } //;0x0200 TPU0_TGI0C void INT_Excep_TPU0_TGI0C(void){ } //;0x0204 TPU0_TGI0D void INT_Excep_TPU0_TGI0D(void){ } //;0x0208 TPU1_TGI1A void INT_Excep_TPU1_TGI1A(void){ } //;0x020C TPU1_TGI1B void INT_Excep_TPU1_TGI1B(void){ } //;0x0210 TPU2_TGI2A void INT_Excep_TPU2_TGI2A(void){ } //;0x0214 TPU2_TGI2B void INT_Excep_TPU2_TGI2B(void){ } //;0x0218 TPU3_TGI3A void INT_Excep_TPU3_TGI3A(void){ } //;0x021C TPU3_TGI3B void INT_Excep_TPU3_TGI3B(void){ } //;0x0220 TPU3_TGI3C void INT_Excep_TPU3_TGI3C(void){ } //;0x0224 TPU3_TGI3D void INT_Excep_TPU3_TGI3D(void){ } //;0x0228 TPU4_TGI4A void INT_Excep_TPU4_TGI4A(void){ } //;0x022C TPU4_TGI4B void INT_Excep_TPU4_TGI4B(void){ } //;0x0230 TPU5_TGI5A void INT_Excep_TPU5_TGI5A(void){ } //;0x0234 TPU5_TGI5B void INT_Excep_TPU5_TGI5B(void){ } //;0x0238 TPU6_TGI6A void INT_Excep_TPU6_TGI6A(void){ } //;0x023C TPU6_TGI6B void INT_Excep_TPU6_TGI6B(void){ } //;0x0240 TPU6_TGI6C void INT_Excep_TPU6_TGI6C(void){ } //;0x0244 TPU6_TGI6D void INT_Excep_TPU6_TGI6D(void){ } //;0x0238 MTU0_TGIA0 void INT_Excep_MTU0_TGIA0(void){ } //;0x023C MTU0_TGIB0 void INT_Excep_MTU0_TGIB0(void){ } //;0x0240 MTU0_TGIC0 void INT_Excep_MTU0_TGIC0(void){ } //;0x0244 MTU0_TGID0 void INT_Excep_MTU0_TGID0(void){ } //;0x0248 MTU0_TGIE0 void INT_Excep_MTU0_TGIE0(void){ } //;0x024C MTU0_TGIF0 void INT_Excep_MTU0_TGIF0(void){ } //;0x0250 TPU7_TGI7A void INT_Excep_TPU7_TGI7A(void){ } //;0x0254 TPU7_TGI7B void INT_Excep_TPU7_TGI7B(void){ } //;0x0250 MTU1_TGIA1 void INT_Excep_MTU1_TGIA1(void){ } //;0x0254 MTU1_TGIB1 void INT_Excep_MTU1_TGIB1(void){ } //;0x0258 TPU8_TGI8A void INT_Excep_TPU8_TGI8A(void){ } //;0x025C TPU8_TGI8B void INT_Excep_TPU8_TGI8B(void){ } //;0x0258 MTU2_TGIA2 void INT_Excep_MTU2_TGIA2(void){ } //;0x025C MTU2_TGIB2 void INT_Excep_MTU2_TGIB2(void){ } //;0x0260 TPU9_TGI9A void INT_Excep_TPU9_TGI9A(void){ } //;0x0264 TPU9_TGI9B void INT_Excep_TPU9_TGI9B(void){ } //;0x0268 TPU9_TGI9C void INT_Excep_TPU9_TGI9C(void){ } //;0x026C TPU9_TGI9D void INT_Excep_TPU9_TGI9D(void){ } //;0x0260 MTU3_TGIA3 void INT_Excep_MTU3_TGIA3(void){ } //;0x0264 MTU3_TGIB3 void INT_Excep_MTU3_TGIB3(void){ } //;0x0268 MTU3_TGIC3 void INT_Excep_MTU3_TGIC3(void){ } //;0x026C MTU3_TGID3 void INT_Excep_MTU3_TGID3(void){ } //;0x0270 TPU10_TGI10A void INT_Excep_TPU10_TGI10A(void){ } //;0x0274 TPU10_TGI10B void INT_Excep_TPU10_TGI10B(void){ } //;0x0270 MTU4_TGIA4 void INT_Excep_MTU4_TGIA4(void){ } //;0x0274 MTU4_TGIB4 void INT_Excep_MTU4_TGIB4(void){ } //;0x0278 MTU4_TGIC4 void INT_Excep_MTU4_TGIC4(void){ } //;0x027C MTU4_TGID4 void INT_Excep_MTU4_TGID4(void){ } //;0x0280 MTU4_TGIV4 void INT_Excep_MTU4_TGIV4(void){ } //;0x0284 MTU5_TGIU5 void INT_Excep_MTU5_TGIU5(void){ } //;0x0288 MTU5_TGIV5 void INT_Excep_MTU5_TGIV5(void){ } //;0x028C MTU5_TGIW5 void INT_Excep_MTU5_TGIW5(void){ } //;0x0290 TPU11_TGI11A void INT_Excep_TPU11_TGI11A(void){ } //;0x0294 TPU11_TGI11B void INT_Excep_TPU11_TGI11B(void){ } //;0x0298 POE_OEI1 void INT_Excep_POE_OEI1(void){ } //;0x029C POE_OEI2 void INT_Excep_POE_OEI2(void){ } //;0x02A0 Reserved //;0x02A4 Reserved //;0x02A8 TMR0_CMIA0 void INT_Excep_TMR0_CMIA0(void){ } //;0x02AC TMR0_CMIB0 void INT_Excep_TMR0_CMIB0(void){ } //;0x02B0 TMR0_OVI0 void INT_Excep_TMR0_OVI0(void){ } //;0x02B4 TMR1_CMIA1 void INT_Excep_TMR1_CMIA1(void){ } //;0x02B8 TMR1_CMIB1 void INT_Excep_TMR1_CMIB1(void){ } //;0x02BC TMR1_OVI1 void INT_Excep_TMR1_OVI1(void){ } //;0x02C0 TMR2_CMIA2 void INT_Excep_TMR2_CMIA2(void){ } //;0x02C4 TMR2_CMIB2 void INT_Excep_TMR2_CMIB2(void){ } //;0x02C8 TMR2_OVI2 void INT_Excep_TMR2_OVI2(void){ } //;0x02CC TMR3_CMIA3 void INT_Excep_TMR3_CMIA3(void){ } //;0x02D0 TMR3_CMIB3 void INT_Excep_TMR3_CMIB3(void){ } //;0x02D4 TMR3_OVI3 void INT_Excep_TMR3_OVI3(void){ } //;0x02D8 RIIC0_EEI0 void INT_Excep_RIIC0_EEI0(void){ } //;0x02DC RIIC0_RXI0 void INT_Excep_RIIC0_RXI0(void){ } //;0x02E0 RIIC0_TXI0 void INT_Excep_RIIC0_TXI0(void){ } //;0x02E4 RIIC0_TEI0 void INT_Excep_RIIC0_TEI0(void){ } //;0x02E8 RIIC1_EEI1 void INT_Excep_RIIC1_EEI1(void){ } //;0x02EC RIIC1_RXI1 void INT_Excep_RIIC1_RXI1(void){ } //;0x02F0 RIIC1_TXI1 void INT_Excep_RIIC1_TXI1(void){ } //;0x02F4 RIIC1_TEI1 void INT_Excep_RIIC1_TEI1(void){ } //;0x02F8 RIIC2_EEI2 void INT_Excep_RIIC2_EEI2(void){ } //;0x02FC RIIC2_RXI2 void INT_Excep_RIIC2_RXI2(void){ } //;0x0300 RIIC2_TXI2 void INT_Excep_RIIC2_TXI2(void){ } //;0x0304 RIIC2_TEI2 void INT_Excep_RIIC2_TEI2(void){ } //;0x0308 RIIC3_EEI3 void INT_Excep_RIIC3_EEI3(void){ } //;0x030C RIIC3_RXI3 void INT_Excep_RIIC3_RXI3(void){ } //;0x0310 RIIC3_TXI3 void INT_Excep_RIIC3_TXI3(void){ } //;0x0314 RIIC3_TEI3 void INT_Excep_RIIC3_TEI3(void){ } //;0x0318 DMACA_DMAC0I void INT_Excep_DMACA_DMAC0I(void){ } //;0x031C DMACA_DMAC1I void INT_Excep_DMACA_DMAC1I(void){ } //;0x0320 DMACA_DMAC2I void INT_Excep_DMACA_DMAC2I(void){ } //;0x0324 DMACA_DMAC3I void INT_Excep_DMACA_DMAC3I(void){ } //;0x0328 Reserved //;0x032C Reserved //;0x0330 Reserved //;0x0334 Reserved //;0x0338 Reserved //;0x033C Reserved //;0x0340 Reserved //;0x0344 Reserved //;0x0348 Reserved //;0x034C Reserved //;0x0350 Reserved //;0x0354 Reserved //;0x0358 SCI0_RXI0 void INT_Excep_SCI0_RXI0(void){ } //;0x035C SCI0_TXI0 void INT_Excep_SCI0_TXI0(void){ } //;0x0360 SCI0_TEI0 void INT_Excep_SCI0_TEI0(void){ } //;0x0364 SCI1_RXI1 void INT_Excep_SCI1_RXI1(void){ } //;0x0368 SCI1_TXI1 void INT_Excep_SCI1_TXI1(void){ } //;0x036C SCI1_TEI1 void INT_Excep_SCI1_TEI1(void){ } //;0x0370 SCI2_RXI2 void INT_Excep_SCI2_RXI2(void){ } //;0x0374 SCI2_TXI2 void INT_Excep_SCI2_TXI2(void){ } //;0x0378 SCI2_TEI2 void INT_Excep_SCI2_TEI2(void){ } //;0x037C SCI3_RXI3 void INT_Excep_SCI3_RXI3(void){ } //;0x0380 SCI3_TXI3 void INT_Excep_SCI3_TXI3(void){ } //;0x0384 SCI3_TEI3 void INT_Excep_SCI3_TEI3(void){ } //;0x0388 SCI4_RXI4 void INT_Excep_SCI4_RXI4(void){ } //;0x038C SCI4_TXI4 void INT_Excep_SCI4_TXI4(void){ } //;0x0390 _SCI4_TEI4 void INT_Excep_SCI4_TEI4(void){ } //;0x0394 SCI5_RXI5 void INT_Excep_SCI5_RXI5(void){ } //;0x0398 SCI5_TXI5 void INT_Excep_SCI5_TXI5(void){ } //;0x039C SCI5_TEI5 void INT_Excep_SCI5_TEI5(void){ } //;0x03A0 SCI6_RXI6 void INT_Excep_SCI6_RXI6(void){ } //;0x03A4 SCI6_TXI6 void INT_Excep_SCI6_TXI6(void){ } //;0x03A8 SCI6_TEI6 void INT_Excep_SCI6_TEI6(void){ } //;0x03AC SCI7_RXI7 void INT_Excep_SCI7_RXI7(void){ } //;0x03B0 SCI7_TXI7 void INT_Excep_SCI7_TXI7(void){ } //;0x03B4 SCI7_TEI7 void INT_Excep_SCI7_TEI7(void){ } //;0x03B8 SCI8_RXI8 void INT_Excep_SCI8_RXI8(void){ } //;0x03BC SCI8_TXI8 void INT_Excep_SCI8_TXI8(void){ } //;0x03C0 SCI8_TEI8 void INT_Excep_SCI8_TEI8(void){ } //;0x03C4 SCI9_RXI9 void INT_Excep_SCI9_RXI9(void){ } //;0x03C8 SCI9_TXI9 void INT_Excep_SCI9_TXI9(void){ } //;0x03CC SCI9_TEI9 void INT_Excep_SCI9_TEI9(void){ } //;0x03D0 SCI10_RXI10 void INT_Excep_SCI10_RXI10(void){ } //;0x03D4 SCI10_TXI10 void INT_Excep_SCI10_TXI10(void){ } //;0x03D8 SCI10_TEI10 void INT_Excep_SCI10_TEI10(void){ } //;0x03DC SCI11_RXI11 void INT_Excep_SCI11_RXI11(void){ } //;0x03E0 SCI11_TXI11 void INT_Excep_SCI11_TXI11(void){ } //;0x03E4 SCI11_TEI11 void INT_Excep_SCI11_TEI11(void){ } //;0x03E8 SCI12_RXI12 void INT_Excep_SCI12_RXI12(void){ } //;0x03EC SCI12_TXI12 void INT_Excep_SCI12_TXI12(void){ } //;0x03F0 SCI12_TEI12 void INT_Excep_SCI12_TEI12(void){ } //;0x03F4 IEB_IEBINT void INT_Excep_IEB_IEBINT(void){ } //;0x03F8 Reserved //;0x03FC Reserved

　2004.05 /************************************************************************ * * Device : RX/RX600/RX630 * * File Name : ioedfine.h * * Abstract : Definition of I/O Register. * * History : 0.10 (2011-04-06) * * NOTE : THIS IS A TYPICAL EXAMPLE. * * ************************************************************************/ #ifndef IODEFINE_H #define IODEFINE_H #endif

　/***********************************************************************/ /* */ /* FILE :interrupt_handlers.h */ /* DATE :Thu, Jan 20, 2011 */ /* DESCRIPTION :Interrupt Handler Declarations */ /* CPU TYPE :RX630 */ /* */ /* This file is generated by KPIT GNU Project Generator. */ /* */ /***********************************************************************/ #ifndef INTERRUPT_HANDLERS_H #define INTERRUPT_HANDLERS_H // Exception(Supervisor Instruction) void INT_Excep_SuperVisorInst(void) __attribute__ ((interrupt)); // Exception(Undefined Instruction) void INT_Excep_UndefinedInst(void) __attribute__ ((interrupt)); // Exception(Floating Point) void INT_Excep_FloatingPoint(void) __attribute__ ((interrupt)); // NMI void INT_NonMaskableInterrupt(void) __attribute__ ((interrupt)); // Dummy void Dummy (void) __attribute__ ((interrupt)); // BRK void INT_Excep_BRK(void) __attribute__ ((interrupt)); //;0x0000 Reserved //;0x0004 Reserved //;0x0008 Reserved //;0x000C Reserved //;0x0010 Reserved //;0x0014 Reserved //;0x0018 Reserved //;0x001C Reserved //;0x0020 Reserved //;0x0024 Reserved //;0x0028 Reserved //;0x002C Reserved //;0x0030 Reserved //;0x0034 Reserved //;0x0038 Reserved //;0x003C Reserved //;0x0040 BUSERR void INT_Excep_BUSERR(void) __attribute__ ((interrupt)); //;0x0044 Reserved //;0x0048 Reserved //;0x004C Reserved //;0x0050 Reserved //;0x0054 FCUERR void INT_Excep_FCU_FCUERR(void) __attribute__ ((interrupt)); //;0x0058 Reserved //;0x005C FRDYI void INT_Excep_FCU_FRDYI(void) __attribute__ ((interrupt)); //;0x0060 Reserved //;0x0064 Reserved //;0x0068 Reserved //;0x006C ICU_SWINT void INT_Excep_ICU_SWINT(void) __attribute__ ((interrupt)); //;0x0070 CMTU0_CMI0 void INT_Excep_CMTU0_CMI0(void) __attribute__ ((interrupt)); //;0x0074 CMTU0_CMI1 void INT_Excep_CMTU0_CMI1(void) __attribute__ ((interrupt)); //;0x0078 CMTU1_CMI2 void INT_Excep_CMTU1_CMI2(void) __attribute__ ((interrupt)); //;0x007C CMTU1_CMI3 void INT_Excep_CMTU1_CMI3(void) __attribute__ ((interrupt)); //;0x0080 Reserved //;0x0084 USB0_D0FIFO0 void INT_Excep_USB0_D0FIFO0(void) __attribute__ ((interrupt)); //;0x0088 USB0_D1FIFO0 void INT_Excep_USB0_D1FIFO0(void) __attribute__ ((interrupt)); //;0x008C USB0_USBI0 void INT_Excep_USB0_USBI0(void) __attribute__ ((interrupt)); //;0x0090 Reserved //;0x0094 Reserved //;0x0098 Reserved //;0x009C RSPI0_SPRI0 void INT_Excep_RSPI0_SPRI0(void) __attribute__ ((interrupt)); //;0x00A0 RSPI0_SPTI0 void INT_Excep_RSPI0_SPTI0(void) __attribute__ ((interrupt)); //;0x00A4 RSPI0_SPII0 void INT_Excep_RSPI0_SPII0(void) __attribute__ ((interrupt)); //;0x00A8 RSPI1_SPRI1 void INT_Excep_RSPI1_SPRI1(void) __attribute__ ((interrupt)); //;0x00AC RSPI1_SPTI1 void INT_Excep_RSPI1_SPTI1(void) __attribute__ ((interrupt)); //;0x00B0 RSPI1_SPII1 void INT_Excep_RSPI1_SPII1(void) __attribute__ ((interrupt)); //;0x00B4 RSPI2_SPRI2 void INT_Excep_RSPI2_SPRI2(void) __attribute__ ((interrupt)); //;0x00B8 RSPI2_SPTI2 void INT_Excep_RSPI2_SPTI2(void) __attribute__ ((interrupt)); //;0x00BC RSPI2_SPII2 void INT_Excep_RSPI2_SPII2(void) __attribute__ ((interrupt)); //;0x00C0 CAN0_RXF0 void INT_Excep_CAN0_RXF0(void) __attribute__ ((interrupt)); //;0x00C4 CAN0_TXF0 void INT_Excep_CAN0_TXF0(void) __attribute__ ((interrupt)); //;0x00C8 CAN0_RXM0 void INT_Excep_CAN0_RXM0(void) __attribute__ ((interrupt)); //;0x00CC CAN0_TXM0 void INT_Excep_CAN0_TXM0(void) __attribute__ ((interrupt)); //;0x00D0 CAN1_RXF1 void INT_Excep_CAN1_RXF1(void) __attribute__ ((interrupt)); //;0x00D4 CAN1_TXF1 void INT_Excep_CAN1_TXF1(void) __attribute__ ((interrupt)); //;0x00D8 CAN1_RXM1 void INT_Excep_CAN1_RXM1(void) __attribute__ ((interrupt)); //;0x00DC CAN1_TXM1 void INT_Excep_CAN1_TXM1(void) __attribute__ ((interrupt)); //;0x00E0 CAN2_RXF2 void INT_Excep_CAN2_RXF2(void) __attribute__ ((interrupt)); //;0x00E4 CAN2_TXF2 void INT_Excep_CAN2_TXF2(void) __attribute__ ((interrupt)); //;0x00E8 CAN2_RXM2 void INT_Excep_CAN2_RXM2(void) __attribute__ ((interrupt)); //;0x00EC CAN2_TXM2 void INT_Excep_CAN2_TXM2(void) __attribute__ ((interrupt)); //;0x00F0 Reserved //;0x00F4 Reserved //;0x00F8 RTC_COUNTUP void INT_Excep_RTC_COUNTUP(void) __attribute__ ((interrupt)); //;0x00FC Reserved //;0x0100 IRQ0 void INT_Excep_IRQ0(void) __attribute__ ((interrupt)); //;0x0104 IRQ1 void INT_Excep_IRQ1(void) __attribute__ ((interrupt)); //;0x0108 IRQ2 void INT_Excep_IRQ2(void) __attribute__ ((interrupt)); //;0x010C IRQ3 void INT_Excep_IRQ3(void) __attribute__ ((interrupt)); //;0x0110 IRQ4 void INT_Excep_IRQ4(void) __attribute__ ((interrupt)); //;0x0114 IRQ5 void INT_Excep_IRQ5(void) __attribute__ ((interrupt)); //;0x0118 IRQ6 void INT_Excep_IRQ6(void) __attribute__ ((interrupt)); //;0x011C IRQ7 void INT_Excep_IRQ7(void) __attribute__ ((interrupt)); //;0x0120 IRQ8 void INT_Excep_IRQ8(void) __attribute__ ((interrupt)); //;0x0124 IRQ9 void INT_Excep_IRQ9(void) __attribute__ ((interrupt)); //;0x0128 IRQ10 void INT_Excep_IRQ10(void) __attribute__ ((interrupt)); //;0x012C IRQ11 void INT_Excep_IRQ11(void) __attribute__ ((interrupt)); //;0x0130 IRQ12 void INT_Excep_IRQ12(void) __attribute__ ((interrupt)); //;0x0134 IRQ13 void INT_Excep_IRQ13(void) __attribute__ ((interrupt)); //;0x0138 IRQ14 void INT_Excep_IRQ14(void) __attribute__ ((interrupt)); //;0x013C IRQ15 void INT_Excep_IRQ15(void) __attribute__ ((interrupt)); //;0x0140 Reserved //;0x0144 Reserved //;0x0148 Reserved //;0x014C Reserved //;0x0150 Reserved //;0x0154 Reserved //;0x0158 Reserved //;0x015C Reserved //;0x0160 Reserved //;0x0164 Reserved //;0x0168 USB_USBR0 void INT_Excep_USB_USBR0(void) __attribute__ ((interrupt)); //;0x016C Reserved //;0x0170 RTC_ALARM void INT_Excep_RTC_ALARM(void) __attribute__ ((interrupt)); //;0x0174 RTC_PRD void INT_Excep_RTC_PRD(void) __attribute__ ((interrupt)); //;0x0178 Reserved //;0x017C Reserved //;0x0180 Reserved //;0x0184 Reserved //;0x0188 AD0_ADI0 void INT_Excep_AD0_ADI0(void) __attribute__ ((interrupt)); //;0x018C Reserved //;0x0190 Reserved //;0x0194 Reserved //;0x0198 S12AD0_S12ADI0 void INT_Excep_S12AD0_S12ADI0(void) __attribute__ ((interrupt)); //;0x019C Reserved //;0x01A0 Reserved //;0x01A4 Reserved //;0x01A8 ICU_GE0 void INT_Excep_ICU_GE0(void) __attribute__ ((interrupt)); //;0x01AC ICU_GE1 void INT_Excep_ICU_GE1(void) __attribute__ ((interrupt)); //;0x01B0 ICU_GE2 void INT_Excep_ICU_GE2(void) __attribute__ ((interrupt)); //;0x01B4 ICU_GE3 void INT_Excep_ICU_GE3(void) __attribute__ ((interrupt)); //;0x01B8 ICU_GE4 void INT_Excep_ICU_GE4(void) __attribute__ ((interrupt)); //;0x01BC ICU_GE5 void INT_Excep_ICU_GE5(void) __attribute__ ((interrupt)); //;0x01C0 ICU_GE6 void INT_Excep_ICU_GE6(void) __attribute__ ((interrupt)); //;0x01C4 Reserved //;0x01C8 ICU_GL0 void INT_Excep_ICU_GL0(void) __attribute__ ((interrupt)); //;0x01CC Reserved //;0x01D0 Reserved //;0x01D4 Reserved //;0x01D8 Reserved //;0x01DC Reserved //;0x01E0 Reserved //;0x01E4 Reserved //;0x01E8 SCIX_SCIX0 void INT_Excep_SCIX_SCIX0(void) __attribute__ ((interrupt)); //;0x01EC SCIX_SCIX1 void INT_Excep_SCIX_SCIX1(void) __attribute__ ((interrupt)); //;0x01F0 SCIX_SCIX2 void INT_Excep_SCIX_SCIX2(void) __attribute__ ((interrupt)); //;0x01F4 SCIX_SCIX3 void INT_Excep_SCIX_SCIX3(void) __attribute__ ((interrupt)); //;0x01F8 TPU0_TGI0A void INT_Excep_TPU0_TGI0A(void) __attribute__ ((interrupt)); //;0x01FC TPU0_TGI0B void INT_Excep_TPU0_TGI0B(void) __attribute__ ((interrupt)); //;0x0200 TPU0_TGI0C void INT_Excep_TPU0_TGI0C(void) __attribute__ ((interrupt)); //;0x0204 TPU0_TGI0D void INT_Excep_TPU0_TGI0D(void) __attribute__ ((interrupt)); //;0x0208 TPU1_TGI1A void INT_Excep_TPU1_TGI1A(void) __attribute__ ((interrupt)); //;0x020C TPU1_TGI1B void INT_Excep_TPU1_TGI1B(void) __attribute__ ((interrupt)); //;0x0210 TPU2_TGI2A void INT_Excep_TPU2_TGI2A(void) __attribute__ ((interrupt)); //;0x0214 TPU2_TGI2B void INT_Excep_TPU2_TGI2B(void) __attribute__ ((interrupt)); //;0x0218 TPU3_TGI3A void INT_Excep_TPU3_TGI3A(void) __attribute__ ((interrupt)); //;0x021C TPU3_TGI3B void INT_Excep_TPU3_TGI3B(void) __attribute__ ((interrupt)); //;0x0220 TPU3_TGI3C void INT_Excep_TPU3_TGI3C(void) __attribute__ ((interrupt)); //;0x0224 TPU3_TGI3D void INT_Excep_TPU3_TGI3D(void) __attribute__ ((interrupt)); //;0x0228 TPU4_TGI4A void INT_Excep_TPU4_TGI4A(void) __attribute__ ((interrupt)); //;0x022C TPU4_TGI4B void INT_Excep_TPU4_TGI4B(void) __attribute__ ((interrupt)); //;0x0230 TPU5_TGI5A void INT_Excep_TPU5_TGI5A(void) __attribute__ ((interrupt)); //;0x0234 TPU5_TGI5B void INT_Excep_TPU5_TGI5B(void) __attribute__ ((interrupt)); //;0x0238 TPU6_TGI6A void INT_Excep_TPU6_TGI6A(void) __attribute__ ((interrupt)); //;0x023C TPU6_TGI6B void INT_Excep_TPU6_TGI6B(void) __attribute__ ((interrupt)); //;0x0240 TPU6_TGI6C void INT_Excep_TPU6_TGI6C(void) __attribute__ ((interrupt)); //;0x0244 TPU6_TGI6D void INT_Excep_TPU6_TGI6D(void) __attribute__ ((interrupt)); //;0x0238 MTU0_TGIA0 void INT_Excep_MTU0_TGIA0(void) __attribute__ ((interrupt)); //;0x023C MTU0_TGIB0 void INT_Excep_MTU0_TGIB0(void) __attribute__ ((interrupt)); //;0x0240 MTU0_TGIC0 void INT_Excep_MTU0_TGIC0(void) __attribute__ ((interrupt)); //;0x0244 MTU0_TGID0 void INT_Excep_MTU0_TGID0(void) __attribute__ ((interrupt)); //;0x0248 MTU0_TGIE0 void INT_Excep_MTU0_TGIE0(void) __attribute__ ((interrupt)); //;0x024C MTU0_TGIF0 void INT_Excep_MTU0_TGIF0(void) __attribute__ ((interrupt)); //;0x0250 TPU7_TGI7A void INT_Excep_TPU7_TGI7A(void) __attribute__ ((interrupt)); //;0x0254 TPU7_TGI7B void INT_Excep_TPU7_TGI7B(void) __attribute__ ((interrupt)); //;0x0250 MTU1_TGIA1 void INT_Excep_MTU1_TGIA1(void) __attribute__ ((interrupt)); //;0x0254 MTU1_TGIB1 void INT_Excep_MTU1_TGIB1(void) __attribute__ ((interrupt)); //;0x0258 TPU8_TGI8A void INT_Excep_TPU8_TGI8A(void) __attribute__ ((interrupt)); //;0x025C TPU8_TGI8B void INT_Excep_TPU8_TGI8B(void) __attribute__ ((interrupt)); //;0x0258 MTU2_TGIA2 void INT_Excep_MTU2_TGIA2(void) __attribute__ ((interrupt)); //;0x025C MTU2_TGIB2 void INT_Excep_MTU2_TGIB2(void) __attribute__ ((interrupt)); //;0x0260 TPU9_TGI9A void INT_Excep_TPU9_TGI9A(void) __attribute__ ((interrupt)); //;0x0264 TPU9_TGI9B void INT_Excep_TPU9_TGI9B(void) __attribute__ ((interrupt)); //;0x0268 TPU9_TGI9C void INT_Excep_TPU9_TGI9C(void) __attribute__ ((interrupt)); //;0x026C TPU9_TGI9D void INT_Excep_TPU9_TGI9D(void) __attribute__ ((interrupt)); //;0x0260 MTU3_TGIA3 void INT_Excep_MTU3_TGIA3(void) __attribute__ ((interrupt)); //;0x0264 MTU3_TGIB3 void INT_Excep_MTU3_TGIB3(void) __attribute__ ((interrupt)); //;0x0268 MTU3_TGIC3 void INT_Excep_MTU3_TGIC3(void) __attribute__ ((interrupt)); //;0x026C MTU3_TGID3 void INT_Excep_MTU3_TGID3(void) __attribute__ ((interrupt)); //;0x0270 TPU10_TGI10A void INT_Excep_TPU10_TGI10A(void) __attribute__ ((interrupt)); //;0x0274 TPU10_TGI10B void INT_Excep_TPU10_TGI10B(void) __attribute__ ((interrupt)); //;0x0270 MTU4_TGIA4 void INT_Excep_MTU4_TGIA4(void) __attribute__ ((interrupt)); //;0x0274 MTU4_TGIB4 void INT_Excep_MTU4_TGIB4(void) __attribute__ ((interrupt)); //;0x0278 MTU4_TGIC4 void INT_Excep_MTU4_TGIC4(void) __attribute__ ((interrupt)); //;0x027C MTU4_TGID4 void INT_Excep_MTU4_TGID4(void) __attribute__ ((interrupt)); //;0x0280 MTU4_TGIV4 void INT_Excep_MTU4_TGIV4(void) __attribute__ ((interrupt)); //;0x0284 MTU5_TGIU5 void INT_Excep_MTU5_TGIU5(void) __attribute__ ((interrupt)); //;0x0288 MTU5_TGIV5 void INT_Excep_MTU5_TGIV5(void) __attribute__ ((interrupt)); //;0x028C MTU5_TGIW5 void INT_Excep_MTU5_TGIW5(void) __attribute__ ((interrupt)); //;0x0290 TPU11_TGI11A void INT_Excep_TPU11_TGI11A(void) __attribute__ ((interrupt)); //;0x0294 TPU11_TGI11B void INT_Excep_TPU11_TGI11B(void) __attribute__ ((interrupt)); //;0x0298 POE_OEI1 void INT_Excep_POE_OEI1(void) __attribute__ ((interrupt)); //;0x029C POE_OEI2 void INT_Excep_POE_OEI2(void) __attribute__ ((interrupt)); //;0x02A0 Reserved //;0x02A4 Reserved //;0x02A8 TMR0_CMIA0 void INT_Excep_TMR0_CMIA0(void) __attribute__ ((interrupt)); //;0x02AC TMR0_CMIB0 void INT_Excep_TMR0_CMIB0(void) __attribute__ ((interrupt)); //;0x02B0 TMR0_OVI0 void INT_Excep_TMR0_OVI0(void) __attribute__ ((interrupt)); //;0x02B4 TMR1_CMIA1 void INT_Excep_TMR1_CMIA1(void) __attribute__ ((interrupt)); //;0x02B8 TMR1_CMIB1 void INT_Excep_TMR1_CMIB1(void) __attribute__ ((interrupt)); //;0x02BC TMR1_OVI1 void INT_Excep_TMR1_OVI1(void) __attribute__ ((interrupt)); //;0x02C0 TMR2_CMIA2 void INT_Excep_TMR2_CMIA2(void) __attribute__ ((interrupt)); //;0x02C4 TMR2_CMIB2 void INT_Excep_TMR2_CMIB2(void) __attribute__ ((interrupt)); //;0x02C8 TMR2_OVI2 void INT_Excep_TMR2_OVI2(void) __attribute__ ((interrupt)); //;0x02CC TMR3_CMIA3 void INT_Excep_TMR3_CMIA3(void) __attribute__ ((interrupt)); //;0x02D0 TMR3_CMIB3 void INT_Excep_TMR3_CMIB3(void) __attribute__ ((interrupt)); //;0x02D4 TMR3_OVI3 void INT_Excep_TMR3_OVI3(void) __attribute__ ((interrupt)); //;0x02D8 RIIC0_EEI0 void INT_Excep_RIIC0_EEI0(void) __attribute__ ((interrupt)); //;0x02DC RIIC0_RXI0 void INT_Excep_RIIC0_RXI0(void) __attribute__ ((interrupt)); //;0x02E0 RIIC0_TXI0 void INT_Excep_RIIC0_TXI0(void) __attribute__ ((interrupt)); //;0x02E4 RIIC0_TEI0 void INT_Excep_RIIC0_TEI0(void) __attribute__ ((interrupt)); //;0x02E8 RIIC1_EEI1 void INT_Excep_RIIC1_EEI1(void) __attribute__ ((interrupt)); //;0x02EC RIIC1_RXI1 void INT_Excep_RIIC1_RXI1(void) __attribute__ ((interrupt)); //;0x02F0 RIIC1_TXI1 void INT_Excep_RIIC1_TXI1(void) __attribute__ ((interrupt)); //;0x02F4 RIIC1_TEI1 void INT_Excep_RIIC1_TEI1(void) __attribute__ ((interrupt)); //;0x02F8 RIIC2_EEI2 void INT_Excep_RIIC2_EEI2(void) __attribute__ ((interrupt)); //;0x02FC RIIC2_RXI2 void INT_Excep_RIIC2_RXI2(void) __attribute__ ((interrupt)); //;0x0300 RIIC2_TXI2 void INT_Excep_RIIC2_TXI2(void) __attribute__ ((interrupt)); //;0x0304 RIIC2_TEI2 void INT_Excep_RIIC2_TEI2(void) __attribute__ ((interrupt)); //;0x0308 RIIC3_EEI3 void INT_Excep_RIIC3_EEI3(void) __attribute__ ((interrupt)); //;0x030C RIIC3_RXI3 void INT_Excep_RIIC3_RXI3(void) __attribute__ ((interrupt)); //;0x0310 RIIC3_TXI3 void INT_Excep_RIIC3_TXI3(void) __attribute__ ((interrupt)); //;0x0314 RIIC3_TEI3 void INT_Excep_RIIC3_TEI3(void) __attribute__ ((interrupt)); //;0x0318 DMACA_DMAC0I void INT_Excep_DMACA_DMAC0I(void) __attribute__ ((interrupt)); //;0x031C DMACA_DMAC1I void INT_Excep_DMACA_DMAC1I(void) __attribute__ ((interrupt)); //;0x0320 DMACA_DMAC2I void INT_Excep_DMACA_DMAC2I(void) __attribute__ ((interrupt)); //;0x0324 DMACA_DMAC3I void INT_Excep_DMACA_DMAC3I(void) __attribute__ ((interrupt)); //;0x0328 Reserved //;0x032C Reserved //;0x0330 Reserved //;0x0334 Reserved //;0x0338 Reserved //;0x033C Reserved //;0x0340 Reserved //;0x0344 Reserved //;0x0348 Reserved //;0x034C Reserved //;0x0350 Reserved //;0x0354 Reserved //;0x0358 SCI0_RXI0 void INT_Excep_SCI0_RXI0(void) __attribute__ ((interrupt)); //;0x035C SCI0_TXI0 void INT_Excep_SCI0_TXI0(void) __attribute__ ((interrupt)); //;0x0360 SCI0_TEI0 void INT_Excep_SCI0_TEI0(void) __attribute__ ((interrupt)); //;0x0364 SCI1_RXI1 void INT_Excep_SCI1_RXI1(void) __attribute__ ((interrupt)); //;0x0368 SCI1_TXI1 void INT_Excep_SCI1_TXI1(void) __attribute__ ((interrupt)); //;0x036C SCI1_TEI1 void INT_Excep_SCI1_TEI1(void) __attribute__ ((interrupt)); //;0x0370 SCI2_RXI2 void INT_Excep_SCI2_RXI2(void) __attribute__ ((interrupt)); //;0x0374 SCI2_TXI2 void INT_Excep_SCI2_TXI2(void) __attribute__ ((interrupt)); //;0x0378 SCI2_TEI2 void INT_Excep_SCI2_TEI2(void) __attribute__ ((interrupt)); //;0x037C SCI3_RXI3 void INT_Excep_SCI3_RXI3(void) __attribute__ ((interrupt)); //;0x0380 SCI3_TXI3 void INT_Excep_SCI3_TXI3(void) __attribute__ ((interrupt)); //;0x0384 SCI3_TEI3 void INT_Excep_SCI3_TEI3(void) __attribute__ ((interrupt)); //;0x0388 SCI4_RXI4 void INT_Excep_SCI4_RXI4(void) __attribute__ ((interrupt)); //;0x038C SCI4_TXI4 void INT_Excep_SCI4_TXI4(void) __attribute__ ((interrupt)); //;0x0390 _SCI4_TEI4 void INT_Excep_SCI4_TEI4(void) __attribute__ ((interrupt)); //;0x0394 SCI5_RXI5 void INT_Excep_SCI5_RXI5(void) __attribute__ ((interrupt)); //;0x0398 SCI5_TXI5 void INT_Excep_SCI5_TXI5(void) __attribute__ ((interrupt)); //;0x039C SCI5_TEI5 void INT_Excep_SCI5_TEI5(void) __attribute__ ((interrupt)); //;0x03A0 SCI6_RXI6 void INT_Excep_SCI6_RXI6(void) __attribute__ ((interrupt)); //;0x03A4 SCI6_TXI6 void INT_Excep_SCI6_TXI6(void) __attribute__ ((interrupt)); //;0x03A8 SCI6_TEI6 void INT_Excep_SCI6_TEI6(void) __attribute__ ((interrupt)); //;0x03AC SCI7_RXI7 void INT_Excep_SCI7_RXI7(void) __attribute__ ((interrupt)); //;0x03B0 SCI7_TXI7 void INT_Excep_SCI7_TXI7(void) __attribute__ ((interrupt)); //;0x03B4 SCI7_TEI7 void INT_Excep_SCI7_TEI7(void) __attribute__ ((interrupt)); //;0x03B8 SCI8_RXI8 void INT_Excep_SCI8_RXI8(void) __attribute__ ((interrupt)); //;0x03BC SCI8_TXI8 void INT_Excep_SCI8_TXI8(void) __attribute__ ((interrupt)); //;0x03C0 SCI8_TEI8 void INT_Excep_SCI8_TEI8(void) __attribute__ ((interrupt)); //;0x03C4 SCI9_RXI9 void INT_Excep_SCI9_RXI9(void) __attribute__ ((interrupt)); //;0x03C8 SCI9_TXI9 void INT_Excep_SCI9_TXI9(void) __attribute__ ((interrupt)); //;0x03CC SCI9_TEI9 void INT_Excep_SCI9_TEI9(void) __attribute__ ((interrupt)); //;0x03D0 SCI10_RXI10 void INT_Excep_SCI10_RXI10(void) __attribute__ ((interrupt)); //;0x03D4 SCI10_TXI10 void INT_Excep_SCI10_TXI10(void) __attribute__ ((interrupt)); //;0x03D8 SCI10_TEI10 void INT_Excep_SCI10_TEI10(void) __attribute__ ((interrupt)); //;0x03DC SCI11_RXI11 void INT_Excep_SCI11_RXI11(void) __attribute__ ((interrupt)); //;0x03E0 SCI11_TXI11 void INT_Excep_SCI11_TXI11(void) __attribute__ ((interrupt)); //;0x03E4 SCI11_TEI11 void INT_Excep_SCI11_TEI11(void) __attribute__ ((interrupt)); //;0x03E8 SCI12_RXI12 void INT_Excep_SCI12_RXI12(void) __attribute__ ((interrupt)); //;0x03EC SCI12_TXI12 void INT_Excep_SCI12_TXI12(void) __attribute__ ((interrupt)); //;0x03F0 SCI12_TEI12 void INT_Excep_SCI12_TEI12(void) __attribute__ ((interrupt)); //;0x03F4 IEB_IEBINT void INT_Excep_IEB_IEBINT(void) __attribute__ ((interrupt)); //;0x03F8 Reserved //;0x03FC Reserved extern void PowerON_Reset(void) __attribute__ ((interrupt)); //;<<VECTOR DATA END (POWER ON RESET)>> #endif

　/***********************************************************************/ /* */ /* FILE :vector_table.c */ /* DATE :Thu, Jan 20, 2011 */ /* DESCRIPTION :Vector Table */ /* CPU TYPE :RX630 */ /* */ /* This file is generated by KPIT GNU Project Generator. */ /* */ /***********************************************************************/ #include "interrupt_handlers.h" typedef void (*fp) (void); extern void PowerON_Reset (void); extern void stack (void); #define FVECT_SECT __attribute__ ((section (".fvectors"))) const void *HardwareVectors[] FVECT_SECT = { //;0xffffffA0 Reserved (fp)0xFFFFFFFF, //;0xffffffA4 Reserved (fp)0xFFFFFFFF, //;0xffffffA8 Reserved (fp)0xFFFFFFFF, //;0xffffffAC Reserved (fp)0xFFFFFFFF, //;0xffffffB0 Reserved (fp)0, //;0xffffffB4 Reserved (fp)0, //;0xffffffB8 Reserved (fp)0, //;0xffffffBC Reserved (fp)0, //;0xffffffC0 Reserved (fp)0, //;0xffffffC4 Reserved (fp)0, //;0xffffffC8 Reserved (fp)0, //;0xffffffCC Reserved (fp)0, //;0xffffffd0 Exception(Supervisor Instruction) INT_Excep_SuperVisorInst, //;0xffffffd4 Reserved (fp)0, //;0xffffffd8 Reserved (fp)0, //;0xffffffdc Exception(Undefined Instruction) INT_Excep_UndefinedInst, //;0xffffffe0 Reserved (fp)0, //;0xffffffe4 Exception(Floating Point) INT_Excep_FloatingPoint, //;0xffffffe8 Reserved (fp)0, //;0xffffffec Reserved (fp)0, //;0xfffffff0 Reserved (fp)0, //;0xfffffff4 Reserved (fp)0, //;0xfffffff8 NMI INT_NonMaskableInterrupt, //;0xfffffffc RESET //;<<VECTOR DATA START (POWER ON RESET)>> //;Power On Reset PowerON_Reset //;<<VECTOR DATA END (POWER ON RESET)>> }; #define RVECT_SECT __attribute__ ((section (".rvectors"))) const fp RelocatableVectors[] RVECT_SECT = { //;0x0000 Reserved (fp)0, //;0x0004 Reserved (fp)0, //;0x0008 Reserved (fp)0, //;0x000C Reserved (fp)0, //;0x0010 Reserved (fp)0, //;0x0014 Reserved (fp)0, //;0x0018 Reserved (fp)0, //;0x001C Reserved (fp)0, //;0x0020 Reserved (fp)0, //;0x0024 Reserved (fp)0, //;0x0028 Reserved (fp)0, //;0x002C Reserved (fp)0, //;0x0030 Reserved (fp)0, //;0x0034 Reserved (fp)0, //;0x0038 Reserved (fp)0, //;0x003C Reserved (fp)0, //;0x0040 BUSERR (fp)INT_Excep_BUSERR, //;0x0044 Reserved (fp)0, //;0x0048 Reserved (fp)0, //;0x004C Reserved (fp)0, //;0x0050 Reserved (fp)0, //;0x0054 FCUERR (fp)INT_Excep_FCU_FCUERR, //;0x0058 Reserved (fp)0, //;0x005C FRDYI (fp)INT_Excep_FCU_FRDYI, //;0x0060 Reserved (fp)0, //;0x0064 Reserved (fp)0, //;0x0068 Reserved (fp)0, //;0x006C ICU_SWINT (fp)INT_Excep_ICU_SWINT, //;0x0070 CMTU0_CMI0 (fp)INT_Excep_CMTU0_CMI0, //;0x0074 CMTU0_CMI1 (fp)INT_Excep_CMTU0_CMI1, //;0x0078 CMTU1_CMI2 (fp)INT_Excep_CMTU1_CMI2, //;0x007C CMTU1_CMI3 (fp)INT_Excep_CMTU1_CMI3, //;0x0080 Reserved (fp)0, //;0x0084 USB0_D0FIFO0 (fp)INT_Excep_USB0_D0FIFO0, //;0x0088 USB0_D1FIFO0 (fp)INT_Excep_USB0_D1FIFO0, //;0x008C USB0_USBI0 (fp)INT_Excep_USB0_USBI0, //;0x0090 Reserved (fp)0, //;0x0094 Reserved (fp)0, //;0x0098 Reserved (fp)0, //;0x009C RSPI0_SPRI0 (fp)INT_Excep_RSPI0_SPRI0, //;0x00A0 RSPI0_SPTI0 (fp)INT_Excep_RSPI0_SPTI0, //;0x00A4 RSPI0_SPII0 (fp)INT_Excep_RSPI0_SPII0, //;0x00A8 RSPI1_SPRI1 (fp)INT_Excep_RSPI1_SPRI1, //;0x00AC RSPI1_SPTI1 (fp)INT_Excep_RSPI1_SPTI1, //;0x00B0 RSPI1_SPII1 (fp)INT_Excep_RSPI1_SPII1, //;0x00B4 RSPI2_SPRI2 (fp)INT_Excep_RSPI2_SPRI2, //;0x00B8 RSPI2_SPTI2 (fp)INT_Excep_RSPI2_SPTI2, //;0x00BC RSPI2_SPII2 (fp)INT_Excep_RSPI2_SPII2, //;0x00C0 CAN0_RXF0 (fp)INT_Excep_CAN0_RXF0, //;0x00C4 CAN0_TXF0 (fp)INT_Excep_CAN0_TXF0, //;0x00C8 CAN0_RXM0 (fp)INT_Excep_CAN0_RXM0, //;0x00CC CAN0_TXM0 (fp)INT_Excep_CAN0_TXM0, //;0x00D0 CAN1_RXF1 (fp)INT_Excep_CAN1_RXF1, //;0x00D4 CAN1_TXF1 (fp)INT_Excep_CAN1_TXF1, //;0x00D8 CAN1_RXM1 (fp)INT_Excep_CAN1_RXM1, //;0x00DC CAN1_TXM1 (fp)INT_Excep_CAN1_TXM1, //;0x00E0 CAN2_RXF2 (fp)INT_Excep_CAN2_RXF2, //;0x00E4 CAN2_TXF2 (fp)INT_Excep_CAN2_TXF2, //;0x00E8 CAN2_RXM2 (fp)INT_Excep_CAN2_RXM2, //;0x00EC CAN2_TXM2 (fp)INT_Excep_CAN2_TXM2, //;0x00F0 Reserved (fp)0, //;0x00F4 Reserved (fp)0, //;0x00F8 RTC_COUNTUP (fp)INT_Excep_RTC_COUNTUP, //;0x00FC Reserved (fp)0, //;0x0100 IRQ0 (fp)INT_Excep_IRQ0, //;0x0104 IRQ1 (fp)INT_Excep_IRQ1, //;0x0108 IRQ2 (fp)INT_Excep_IRQ2, //;0x010C IRQ3 (fp)INT_Excep_IRQ3, //;0x0110 IRQ4 (fp)INT_Excep_IRQ4, //;0x0114 IRQ5 (fp)INT_Excep_IRQ5, //;0x0118 IRQ6 (fp)INT_Excep_IRQ6, //;0x011C IRQ7 (fp)INT_Excep_IRQ7, //;0x0120 IRQ8 (fp)INT_Excep_IRQ8, //;0x0124 IRQ9 (fp)INT_Excep_IRQ9, //;0x0128 IRQ10 (fp)INT_Excep_IRQ10, //;0x012C IRQ11 (fp)INT_Excep_IRQ11, //;0x0130 IRQ12 (fp)INT_Excep_IRQ12, //;0x0134 IRQ13 (fp)INT_Excep_IRQ13, //;0x0138 IRQ14 (fp)INT_Excep_IRQ14, //;0x013C IRQ15 (fp)INT_Excep_IRQ15, //;0x0140 Reserved (fp)0, //;0x0144 Reserved (fp)0, //;0x0148 Reserved (fp)0, //;0x014C Reserved (fp)0, //;0x0150 Reserved (fp)0, //;0x0154 Reserved (fp)0, //;0x0158 Reserved (fp)0, //;0x015C Reserved (fp)0, //;0x0160 Reserved (fp)0, //;0x0164 Reserved (fp)0, //;0x0168 USB_USBR0 (fp)INT_Excep_USB_USBR0, //;0x016C Reserved (fp)0, //;0x0170 RTC_ALARM (fp)INT_Excep_RTC_ALARM, //;0x0174 RTC_PRD (fp)INT_Excep_RTC_PRD, //;0x0178 Reserved (fp)0, //;0x017C Reserved (fp)0, //;0x0180 Reserved (fp)0, //;0x0184 Reserved (fp)0, //;0x0188 AD0_ADI0 (fp)INT_Excep_AD0_ADI0, //;0x018C Reserved (fp)0, //;0x0190 Reserved (fp)0, //;0x0194 Reserved (fp)0, //;0x0198 S12AD0_S12ADI0 (fp)INT_Excep_S12AD0_S12ADI0, //;0x019C Reserved (fp)0, //;0x01A0 Reserved (fp)0, //;0x01A4 Reserved (fp)0, //;0x01A8 ICU_GE0 (fp)INT_Excep_ICU_GE0, //;0x01AC ICU_GE1 (fp)INT_Excep_ICU_GE1, //;0x01B0 ICU_GE2 (fp)INT_Excep_ICU_GE2, //;0x01B4 ICU_GE3 (fp)INT_Excep_ICU_GE3, //;0x01B8 ICU_GE4 (fp)INT_Excep_ICU_GE4, //;0x01BC ICU_GE5 (fp)INT_Excep_ICU_GE5, //;0x01C0 ICU_GE6 (fp)INT_Excep_ICU_GE6, //;0x01C4 Reserved (fp)0, //;0x01C8 ICU_GL0 (fp)INT_Excep_ICU_GL0, //;0x01CC Reserved (fp)0, //;0x01D0 Reserved (fp)0, //;0x01D4 Reserved (fp)0, //;0x01D8 Reserved (fp)0, //;0x01DC Reserved (fp)0, //;0x01E0 Reserved (fp)0, //;0x01E4 Reserved (fp)0, //;0x01E8 SCIX_SCIX0 (fp)INT_Excep_SCIX_SCIX0, //;0x01EC SCIX_SCIX1 (fp)INT_Excep_SCIX_SCIX1, //;0x01F0 SCIX_SCIX2 (fp)INT_Excep_SCIX_SCIX2, //;0x01F4 SCIX_SCIX3 (fp)INT_Excep_SCIX_SCIX3, //;0x01F8 TPU0_TGI0A (fp)INT_Excep_TPU0_TGI0A, //;0x01FC TPU0_TGI0B (fp)INT_Excep_TPU0_TGI0B, //;0x0200 TPU0_TGI0C (fp)INT_Excep_TPU0_TGI0C, //;0x0204 TPU0_TGI0D (fp)INT_Excep_TPU0_TGI0D, //;0x0208 TPU1_TGI1A (fp)INT_Excep_TPU1_TGI1A, //;0x020C TPU1_TGI1B (fp)INT_Excep_TPU1_TGI1B, //;0x0210 TPU2_TGI2A (fp)INT_Excep_TPU2_TGI2A, //;0x0214 TPU2_TGI2B (fp)INT_Excep_TPU2_TGI2B, //;0x0218 TPU3_TGI3A (fp)INT_Excep_TPU3_TGI3A, //;0x021C TPU3_TGI3B (fp)INT_Excep_TPU3_TGI3B, //;0x0220 TPU3_TGI3C (fp)INT_Excep_TPU3_TGI3C, //;0x0224 TPU3_TGI3D (fp)INT_Excep_TPU3_TGI3D, //;0x0228 TPU4_TGI4A (fp)INT_Excep_TPU4_TGI4A, //;0x022C TPU4_TGI4B (fp)INT_Excep_TPU4_TGI4B, //;0x0230 TPU5_TGI5A (fp)INT_Excep_TPU5_TGI5A, //;0x0234 TPU5_TGI5B (fp)INT_Excep_TPU5_TGI5B, //;0x0238 TPU6_TGI6A (fp)INT_Excep_TPU6_TGI6A, //;0x023C TPU6_TGI6B (fp)INT_Excep_TPU6_TGI6B, //;0x0240 TPU6_TGI6C (fp)INT_Excep_TPU6_TGI6C, //;0x0244 TPU6_TGI6D (fp)INT_Excep_TPU6_TGI6D, //;0x0238 MTU0_TGIA0 // (fp)INT_Excep_MTU0_TGIA0, //;0x023C MTU0_TGIB0 // (fp)INT_Excep_MTU0_TGIB0, //;0x0240 MTU0_TGIC0 // (fp)INT_Excep_MTU0_TGIC0, //;0x0244 MTU0_TGID0 // (fp)INT_Excep_MTU0_TGID0, //;0x0248 MTU0_TGIE0 (fp)INT_Excep_MTU0_TGIE0, //;0x024C MTU0_TGIF0 (fp)INT_Excep_MTU0_TGIF0, //;0x0250 TPU7_TGI7A (fp)INT_Excep_TPU7_TGI7A, //;0x0254 TPU7_TGI7B (fp)INT_Excep_TPU7_TGI7B, //;0x0250 MTU1_TGIA1 // (fp)INT_Excep_MTU1_TGIA1, //;0x0254 MTU1_TGIB1 // (fp)INT_Excep_MTU1_TGIB1, //;0x0258 TPU8_TGI8A (fp)INT_Excep_TPU8_TGI8A, //;0x025C TPU8_TGI8B (fp)INT_Excep_TPU8_TGI8B, //;0x0258 MTU2_TGIA2 // (fp)INT_Excep_MTU2_TGIA2, //;0x025C MTU2_TGIB2 // (fp)INT_Excep_MTU2_TGIB2, //;0x0260 TPU9_TGI9A (fp)INT_Excep_TPU9_TGI9A, //;0x0264 TPU9_TGI9B (fp)INT_Excep_TPU9_TGI9B, //;0x0268 TPU9_TGI9C (fp)INT_Excep_TPU9_TGI9C, //;0x026C TPU9_TGI9D (fp)INT_Excep_TPU9_TGI9D, //;0x0260 MTU3_TGIA3 // (fp)INT_Excep_MTU3_TGIA3, //;0x0264 MTU3_TGIB3 // (fp)INT_Excep_MTU3_TGIB3, //;0x0268 MTU3_TGIC3 // (fp)INT_Excep_MTU3_TGIC3, //;0x026C MTU3_TGID3 // (fp)INT_Excep_MTU3_TGID3, //;0x0270 TPU10_TGI10A (fp)INT_Excep_TPU10_TGI10A, //;0x0274 TPU10_TGI10B (fp)INT_Excep_TPU10_TGI10B, //;0x0270 MTU4_TGIA4 // (fp)INT_Excep_MTU4_TGIA4, //;0x0274 MTU4_TGIB4 // (fp)INT_Excep_MTU4_TGIB4, //;0x0278 MTU4_TGIC4 (fp)INT_Excep_MTU4_TGIC4, //;0x027C MTU4_TGID4 (fp)INT_Excep_MTU4_TGID4, //;0x0280 MTU4_TGIV4 (fp)INT_Excep_MTU4_TGIV4, //;0x0284 MTU5_TGIU5 (fp)INT_Excep_MTU5_TGIU5, //;0x0288 MTU5_TGIV5 (fp)INT_Excep_MTU5_TGIV5, //;0x028C MTU5_TGIW5 (fp)INT_Excep_MTU5_TGIW5, //;0x0290 TPU11_TGI11A (fp)INT_Excep_TPU11_TGI11A, //;0x0294 TPU11_TGI11B (fp)INT_Excep_TPU11_TGI11B, //;0x0298 POE_OEI1 (fp)INT_Excep_POE_OEI1, //;0x029C POE_OEI2 (fp)INT_Excep_POE_OEI2, //;0x02A0 Reserved (fp)0, //;0x02A4 Reserved (fp)0, //;0x02A8 TMR0_CMIA0 (fp)INT_Excep_TMR0_CMIA0, //;0x02AC TMR0_CMIB0 (fp)INT_Excep_TMR0_CMIB0, //;0x02B0 TMR0_OVI0 (fp)INT_Excep_TMR0_OVI0, //;0x02B4 TMR1_CMIA1 (fp)INT_Excep_TMR1_CMIA1, //;0x02B8 TMR1_CMIB1 (fp)INT_Excep_TMR1_CMIB1, //;0x02BC TMR1_OVI1 (fp)INT_Excep_TMR1_OVI1, //;0x02C0 TMR2_CMIA2 (fp)INT_Excep_TMR2_CMIA2, //;0x02C4 TMR2_CMIB2 (fp)INT_Excep_TMR2_CMIB2, //;0x02C8 TMR2_OVI2 (fp)INT_Excep_TMR2_OVI2, //;0x02CC TMR3_CMIA3 (fp)INT_Excep_TMR3_CMIA3, //;0x02D0 TMR3_CMIB3 (fp)INT_Excep_TMR3_CMIB3, //;0x02D4 TMR3_OVI3 (fp)INT_Excep_TMR3_OVI3, //;0x02D8 RIIC0_EEI0 (fp)INT_Excep_RIIC0_EEI0, //;0x02DC RIIC0_RXI0 (fp)INT_Excep_RIIC0_RXI0, //;0x02E0 RIIC0_TXI0 (fp)INT_Excep_RIIC0_TXI0, //;0x02E4 RIIC0_TEI0 (fp)INT_Excep_RIIC0_TEI0, //;0x02E8 RIIC1_EEI1 (fp)INT_Excep_RIIC1_EEI1, //;0x02EC RIIC1_RXI1 (fp)INT_Excep_RIIC1_RXI1, //;0x02F0 RIIC1_TXI1 (fp)INT_Excep_RIIC1_TXI1, //;0x02F4 RIIC1_TEI1 (fp)INT_Excep_RIIC1_TEI1, //;0x02F8 RIIC2_EEI2 (fp)INT_Excep_RIIC2_EEI2, //;0x02FC RIIC2_RXI2 (fp)INT_Excep_RIIC2_RXI2, //;0x0300 RIIC2_TXI2 (fp)INT_Excep_RIIC2_TXI2, //;0x0304 RIIC2_TEI2 (fp)INT_Excep_RIIC2_TEI2, //;0x0308 RIIC3_EEI3 (fp)INT_Excep_RIIC3_EEI3, //;0x030C RIIC3_RXI3 (fp)INT_Excep_RIIC3_RXI3, //;0x0310 RIIC3_TXI3 (fp)INT_Excep_RIIC3_TXI3, //;0x0314 RIIC3_TEI3 (fp)INT_Excep_RIIC3_TEI3, //;0x0318 DMACA_DMAC0I (fp)INT_Excep_DMACA_DMAC0I, //;0x031C DMACA_DMAC1I (fp)INT_Excep_DMACA_DMAC1I, //;0x0320 DMACA_DMAC2I (fp)INT_Excep_DMACA_DMAC2I, //;0x0324 DMACA_DMAC3I (fp)INT_Excep_DMACA_DMAC3I, //;0x0328 Reserved (fp)0, //;0x032C Reserved (fp)0, //;0x0330 Reserved (fp)0, //;0x0334 Reserved (fp)0, //;0x0338 Reserved (fp)0, //;0x033C Reserved (fp)0, //;0x0340 Reserved (fp)0, //;0x0344 Reserved (fp)0, //;0x0348 Reserved (fp)0, //;0x034C Reserved (fp)0, //;0x0350 Reserved (fp)0, //;0x0354 Reserved (fp)0, //;0x0358 SCI0_RXI0 (fp)INT_Excep_SCI0_RXI0, //;0x035C SCI0_TXI0 (fp)INT_Excep_SCI0_TXI0, //;0x0360 SCI0_TEI0 (fp)INT_Excep_SCI0_TEI0, //;0x0364 SCI1_RXI1 (fp)INT_Excep_SCI1_RXI1, //;0x0368 SCI1_TXI1 (fp)INT_Excep_SCI1_TXI1, //;0x036C SCI1_TEI1 (fp)INT_Excep_SCI1_TEI1, //;0x0370 SCI2_RXI2 (fp)INT_Excep_SCI2_RXI2, //;0x0374 SCI2_TXI2 (fp)INT_Excep_SCI2_TXI2, //;0x0378 SCI2_TEI2 (fp)INT_Excep_SCI2_TEI2, //;0x037C SCI3_RXI3 (fp)INT_Excep_SCI3_RXI3, //;0x0380 SCI3_TXI3 (fp)INT_Excep_SCI3_TXI3, //;0x0384 SCI3_TEI3 (fp)INT_Excep_SCI3_TEI3, //;0x0388 SCI4_RXI4 (fp)INT_Excep_SCI4_RXI4, //;0x038C SCI4_TXI4 (fp)INT_Excep_SCI4_TXI4, //;0x0390 _SCI4_TEI4 (fp)INT_Excep_SCI4_TEI4, //;0x0394 SCI5_RXI5 (fp)INT_Excep_SCI5_RXI5, //;0x0398 SCI5_TXI5 (fp)INT_Excep_SCI5_TXI5, //;0x039C SCI5_TEI5 (fp)INT_Excep_SCI5_TEI5, //;0x03A0 SCI6_RXI6 (fp)INT_Excep_SCI6_RXI6, //;0x03A4 SCI6_TXI6 (fp)INT_Excep_SCI6_TXI6, //;0x03A8 SCI6_TEI6 (fp)INT_Excep_SCI6_TEI6, //;0x03AC SCI7_RXI7 (fp)INT_Excep_SCI7_RXI7, //;0x03B0 SCI7_TXI7 (fp)INT_Excep_SCI7_TXI7, //;0x03B4 SCI7_TEI7 (fp)INT_Excep_SCI7_TEI7, //;0x03B8 SCI8_RXI8 (fp)INT_Excep_SCI8_RXI8, //;0x03BC SCI8_TXI8 (fp)INT_Excep_SCI8_TXI8, //;0x03C0 SCI8_TEI8 (fp)INT_Excep_SCI8_TEI8, //;0x03C4 SCI9_RXI9 (fp)INT_Excep_SCI9_RXI9, //;0x03C8 SCI9_TXI9 (fp)INT_Excep_SCI9_TXI9, //;0x03CC SCI9_TEI9 (fp)INT_Excep_SCI9_TEI9, //;0x03D0 SCI10_RXI10 (fp)INT_Excep_SCI10_RXI10, //;0x03D4 SCI10_TXI10 (fp)INT_Excep_SCI10_TXI10, //;0x03D8 SCI10_TEI10 (fp)INT_Excep_SCI10_TEI10, //;0x03DC SCI11_RXI11 (fp)INT_Excep_SCI11_RXI11, //;0x03E0 SCI11_TXI11 (fp)INT_Excep_SCI11_TXI11, //;0x03E4 SCI11_TEI11 (fp)INT_Excep_SCI11_TEI11, //;0x03E8 SCI12_RXI12 (fp)INT_Excep_SCI12_RXI12, //;0x03EC SCI12_TXI12 (fp)INT_Excep_SCI12_TXI12, //;0x03F0 SCI12_TEI12 (fp)INT_Excep_SCI12_TEI12, //;0x03F4 IEB_IEBINT (fp)INT_Excep_IEB_IEBINT, //;0x03F8 Reserved (fp)0, //;0x03FC Reserved (fp)0, };

　/*------------------------------------------------------------------------ | FILE : reset_program.asm | DATE : Tue, Feb 15, 2011 | DESCRIPTION : Reset Program | CPU TYPE : RX610 | | This file is generated by KPIT GNU Project Generator (Ver.4.5). | | ------------------------------------------------------------------------*/ /*reset_program.asm*/ .list .section .text .global _PowerON_Reset /*global Start routine */ .extern _HardwareSetup /*external Sub-routine to initialise Hardware*/ .extern _data .extern _mdata .extern _ebss .extern _bss .extern _edata .extern _main .extern _ustack .extern _istack .extern _rvectors #if DEBUG .extern _exit #endif _PowerON_Reset : /* initialise user stack pointer */ mvtc #_ustack,USP /* initialise interrupt stack pointer */ mvtc #_istack,ISP /* setup intb */ mvtc #_rvectors_start, intb /* INTERRUPT VECTOR ADDRESS definition */ /* setup FPSW */ mvtc #100h, fpsw /* load data section from ROM to RAM */ mov #_mdata,r2 /* src ROM address of data section in R2 */ mov #_data,r1 /* dest start RAM address of data section in R1 */ mov #_edata,r3 /* end RAM address of data section in R3 */ sub r1,r3 /* size of data section in R3 (R3=R3-R1) */ smovf /* block copy R3 bytes from R2 to R1 */ /* bss initialisation : zero out bss */ mov #00h,r2 /* load R2 reg with zero */ mov #_ebss, r3 /* store the end address of bss in R3 */ mov #_bss, r1 /* store the start address of bss in R1 */ sub r1,r3 /* size of bss section in R3 (R3=R3-R1) */ sstr.b /* call the hardware initialiser */ bsr.a _HardwareSetup nop /* setup PSW */ mvtc #10000h, psw /* Set Ubit & Ibit for PSW */ /* change PSW PM to user-mode */ MVFC PSW,R1 OR #00100000h,R1 PUSH.L R1 MVFC PC,R1 ADD #10,R1 PUSH.L R1 RTE NOP NOP #ifdef CPPAPP bsr.a __rx_init #endif /* start user program */ bsr.a _main bsr.a _exit #ifdef CPPAPP .global _rx_run_preinit_array .type _rx_run_preinit_array,@function _rx_run_preinit_array: mov #__preinit_array_start,r1 mov #__preinit_array_end,r2 bra.a _rx_run_inilist .global _rx_run_init_array .type _rx_run_init_array,@function _rx_run_init_array: mov #__init_array_start,r1 mov #__init_array_end,r2 mov #4, r3 bra.a _rx_run_inilist .global _rx_run_fini_array .type _rx_run_fini_array,@function _rx_run_fini_array: mov #__fini_array_start,r2 mov #__fini_array_end,r1 mov #-4, r3 /* fall through */ _rx_run_inilist: next_inilist: cmp r1,r2 beq.b done_inilist mov.l [r1],r4 cmp #-1, r4 beq.b skip_inilist cmp #0, r4 beq.b skip_inilist pushm r1-r3 jsr r4 popm r1-r3 skip_inilist: add r3,r1 bra.b next_inilist done_inilist: rts .section .init,"ax" .balign 4 .global __rx_init __rx_init: .section .fini,"ax" .balign 4 .global __rx_fini __rx_fini: bsr.a _rx_run_fini_array .section .sdata .balign 4 .global __gp .weak __gp __gp: .section .data .global ___dso_handle .weak ___dso_handle ___dso_handle: .long 0 .section .init,"ax" bsr.a _rx_run_preinit_array bsr.a _rx_run_init_array rts .global __rx_init_end __rx_init_end: .section .fini,"ax" rts .global __rx_fini_end __rx_fini_end: #endif /* call to exit*/ _exit: bra _loop_here _loop_here: bra _loop_here .text .end

　[Version] Version=1.0 [Mode] DEFAULT_MODE=99 MODE=99_10 [Memory MAP] MAP_99_00=0x00000000,0x0001FFFF,RAM,64,0101,2 MAP_99_01=0x00080000,0x000FFFFF,I/O,32,0101,2 MAP_99_02=0x00100000,0x00107FFF,ROM,32,0101,2 MAP_99_03=0x007F8000,0x007F9FFF,RAM,32,0101,2 MAP_99_04=0x007FC000,0x007FC4FF,I/O,32,0101,2 MAP_99_05=0x007FFC00,0x007FFFFF,I/O,32,0101,2 MAP_99_06=0x00E80000,0x00FFFFFF,ROM,32,0101,2 MAP_99_07=0xFEFFE000,0xFEFFFFFF,ROM,32,0101,2 MAP_99_08=0xFF7FC000,0xFF7FFFFF,ROM,32,0101,2 MAP_99_09=0xFFE00000,0xFFFFFFFF,ROM,64,0101,2 [Simulator] RESOURCE_99=0x00000000,0x0001FFFF,R/W 0x00080000,0x000FFFFF,R/W 0x007FC000,0x007FC4FF,R/W 0x007FFC00,0x007FFFFF,R/W 0xFFE00000,0xFFFFFFFF,R SIMIOADR=0x0