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　[SH4a-SH7450] INTHandler|0|0||1|0x0000800|0|0|<<CEND>>|<<GEND>>|.text|0|0||1|0x00002000|0|0|0|.text|All-files|<<FEND>>|0|.text.*|All-files|<<FEND>>|1|etext|<<FEND>>|<<CEND>>|<<GEND>>|.init|0|0||0||0|0|0|.init|All-files|<<FEND>>|<<CEND>>|<<GEND>>|.fini|0|0||0||0|0|0|.fini|All-files|<<FEND>>|<<CEND>>|<<GEND>>|.got|0|0||0||0|0|0|.got|All-files|<<FEND>>|0|.got.plt|All-files|<<FEND>>|<<CEND>>|<<GEND>>|.rodata|0|0||0||0|0|0|.rodata|All-files|<<FEND>>|0|.rodata.*|All-files|<<FEND>>|1|_erodata|<<FEND>>|<<CEND>>|<<GEND>>|.eh_frame_hdr|0|0||0||0|0|0|.eh_frame_hdr|All-files|<<FEND>>|<<CEND>>|<<GEND>>|.eh_frame|0|0||0||0|0|0|.eh_frame|All-files|<<FEND>>|<<CEND>>|<<GEND>>|.jcr|0|0||0||0|0|0|.jcr|All-files|<<FEND>>|<<CEND>>|<<GEND>>|.tors|0|0||0||0|0|1|__CTOR_LIST__|<<FEND>>|1|___ctors|<<FEND>>|0|.ctors|All-files|<<FEND>>|1|___ctors_end|<<FEND>>|1|__CTOR_END__|<<FEND>>|1|__DTOR_LIST__|<<FEND>>|1|___dtors|<<FEND>>|0|.dtors|All-files|<<FEND>>|1|___dtors_end|<<FEND>>|1|__DTOR_END__|<<FEND>>|1|_mdata|<<FEND>>|<<CEND>>|<<GEND>>|RSTHandler|0|0||1|0xA0000000|0|0|1|_ResetHandler|<<FEND>>|<<CEND>>|<<GEND>>|.data|0|2|_mdata|1|0xE5200000|0|0|1|_data|<<FEND>>|0|.data|All-files|<<FEND>>|0|.data.*|All-files|<<FEND>>|1|_edata|<<FEND>>|<<CEND>>|<<GEND>>|.gcc_exc|0|0||0||0|0|0|.gcc_exc|All-files|<<FEND>>|<<CEND>>|<<GEND>>|.bss|0|0||0||0|0|1|_bss|<<FEND>>|0|.bss|All-files|<<FEND>>|0|.bss.*|All-files|<<FEND>>|0|COMMON|All-files|<<FEND>>|1|_ebss|<<FEND>>|1|_end|<<FEND>>|<<CEND>>|<<GEND>>|.stack|0|0||1|0xE5202000|0|0|1|_stack|<<FEND>>|<<CEND>>|<<GEND>>

　2012.07 [Files] 1=resetprg\SH4A.asm 2=1 3=DBsct\sh.c 4=IntPRG\sh7450.c 5=vecttbl\sh7450.c 6=lowlvl\sh4.src 7=lowsrc\sh.c 8=sbrk\sh.c 9=iodefine\7450.h 10=vect\sh7450.inc 11=hwsetup\7450.c 12=0 13=0 14=0 15=env\sh7450.s 16=vhandler\sh7450.s 17=Common\Main.c 18=Common\typedefine.h 19=Common\intrinsics.h Asm 11=hwsetup\sh.src Demo 17=Common\Sort.c [CPU Type Data] I/O Stream=20 Heap Size=H'400 Hw Setup Function=HardwareSetup Stack Pointer=H'E5202000 Stack Size=H'400 Summary 0= Summary 1= Summary 2=\n Summary 3=Program start 0x1000. Summary 4=RAM start 0x18000000. [Section] Reset Section=RSTHandler Reset Address=0A0000000 Vector Section=.vects Vector Address=080000400 ResetPRG Section=PResetPRG ResetPRG Address=000001000 Program Section=.text,.rodata Program Address=000002000 B Section=.data,.bss B Address=0E5200000 Stack Section=.stack Stack Address=E5202000 [C++ Section] Reset Section=RSTHandler Reset Address=0A0000000 Vector Section=.vects Vector Address=080000400 ResetPRG Section=PResetPRG ResetPRG Address=000001000 Program Section=.text,.rodata Program Address=000002000 B Section=.data,.bss B Address=0E5200000 Stack Section=.stack Stack Address=E5202000 [Option] Compiler= Assembler= OptLinker= Converter= Librarian=

　 .equ TRA, 0xFF000020 .equ EXPEVT, 0xFF000024 .equ INTEVT, 0xFF000028 .equ EXPMASK,0xFF2F0004

　2009.10 /********************************************************************* * * Device : SH-4A/SH74504,SH74513 * * File Name : hwsetup.c(.cpp) * * Abstract : Hardware Setup file. * * History : 1.00 (2009-10-08) [Hardware Manual Revision : 0.60] * * NOTE : THIS IS A TYPICAL EXAMPLE. * * Copyright(c) 2009 Renesas Technology Corp. * And Renesas Solutions Corp.,All Rights Reserved. * *********************************************************************/ #include "iodefine.h" #ifdef __cplusplus extern "C" { #endif extern void HardwareSetup(void); #ifdef __cplusplus } #endif void HardwareSetup(void) { /* */ }

　 #include "interrupt_handlers.h" //;H'000 PowerON Reset //;H'020 Reserved void INT_Reserved020() { } //;H'040 Data TLB miss exception(read) void INT_TLB_MISS_READ_EXP() { } //;H'060 Data TLB miss exception(write) void INT_TLB_MISS_WRITE_EXP() { } //;H'080 Initial page write exception void INT_TLB_INIT_PAGE_EXP() { } //;H'0A0 Data TLB protection violation exception (read) void INT_TLB_PROTECT_READ_EXP() { } //;H'0C0 Data TLB protection violation exception (write) void INT_TLB_PROTECT_WRITE_EXP() { } //;H'0E0 Data address error(read) void INT_ADR_ERROR_READ() { } //;H'100 Data address error(write) void INT_ADR_ERROR_WRITE() { } //;H'120 FPU exception void INT_FPU_EXP() { } //;H'140 Reserved void INT_Reserved140() { } //;H'160 Unconditional trap(TRAPA) void INT_TRAP() { } //;H'180 General illegal instruction exception void INT_ILLEGAL_INST_EXP() { } //;H'1A0 Slot illegal instruction exception void INT_ILLEGAL_SLOT_EXP() { } //;H'1C0 NMI void INT_NMI() { } //;H'1E0 USER_BREAK void INT_USER_BREAK() { } //;H'200 IRQ IRQ7 void INT_IRQ7() { } //;H'220 Reserved void INT_Reserved220() { } //;H'240 IRQ IRQ0 void INT_IRQ0() { } //;H'260 Reserved void INT_Reserved260() { } //;H'280 IRQ IRQ1 void INT_IRQ1() { } //;H'2A0 Reserved void INT_Reserved2A0() { } //;H'2C0 IRQ IRQ2 void INT_IRQ2() { } //;H'2E0 Reserved void INT_Reserved2E0() { } //;H'300 IRQ IRQ3 void INT_IRQ3() { } //;H'320 Reserved void INT_Reserved320() { } //;H'340 IRQ IRQ4 void INT_IRQ4() { } //;H'360 Reserved void INT_Reserved360() { } //;H'380 IRQ IRQ5 void INT_IRQ5() { } //;H'3A0 Reserved void INT_Reserved3A0() { } //;H'3C0 IRQ IRQ6 void INT_IRQ6() { } //;H'3E0 Reserved void INT_Reserved3E0() { } //;H'400 Reserved void INT_Reserved400() { } //;H'420 Reserved void INT_Reserved420() { } //;H'440 Reserved void INT_Reserved440() { } //;H'460 Reserved void INT_Reserved460() { } //;H'480 Reserved void INT_Reserved480() { } //;H'4A0 Reserved void INT_Reserved4A0() { } //;H'4C0 Reserved void INT_Reserved4C0() { } //;H'4E0 Reserved void INT_Reserved4E0() { } //;H'500 Reserved void INT_Reserved500() { } //;H'520 Reserved void INT_Reserved520() { } //;H'540 Reserved void INT_Reserved540() { } //;H'560 WDT ITI void INT_WDT_ITI() { } //;H'580 TMU0 void INT_TMU0_TUNI0() { } //;H'5A0 TMU1 void INT_TMU1_TUNI1() { } //;H'5C0 TMU2 underflow interrupt void INT_TMU2_TUNI2() { } //;H'5E0 Reserved void INT_Reserved5E0() { } //;H'600 H-UDI interrupt void INT_H_UDI() { } //;H'620 Reserved void INT_Reserved620() { } //;H'640 Reserved void INT_Reserved640() { } //;H'660 Reserved void INT_Reserved660() { } //;H'680 Reserved void INT_Reserved680() { } //;H'6A0 Reserved void INT_Reserved6A0() { } //;H'6C0 Reserved void INT_Reserved6C0() { } //;H'6E0 Reserved void INT_Reserved6E0() { } //;H'700 DMAC_DMINT0 void INT_DMAC_DMINT0() { } //;H'720 DMAC_DMINT1 void INT_DMAC_DMINT1() { } //;H'740 DMAC_DMINT2 void INT_DMAC_DMINT2() { } //;H'760 DMAC_DMINT3 void INT_DMAC_DMINT3() { } //;H'780 DMAC_DMAE0 void INT_DMAC_DMAE0() { } //;H'7A0 DMAC_DMAE1 void INT_DMAC_DMAE1() { } //;H'7C0 DMAC_DMINT4 void INT_DMAC_DMINT4() { } //;H'7E0 Reserved void INT_Reserved7E0() { } //;H'800 General fpu disable exception void INT_FPU_DISABLE_EXP() { } //;H'820 Slot fpu disable exception void INT_FPU_SLOT_DISABLE_EXP() { } //;H'840 DMAC_DMINT5 void INT_DMAC_DMINT5() { } //;H'860 DMAC_DMINT6 void INT_DMAC_DMINT6() { } //;H'880 DMAC_DMINT7 void INT_DMAC_DMINT7() { } //;H'8A0 DMAC_DMINT8 void INT_DMAC_DMINT8() { } //;H'8C0 DMAC_DMINT9 void INT_DMAC_DMINT9() { } //;H'8E0 DMAC_DMINT10 void INT_DMAC_DMINT10() { } //;H'900 DMAC_DMINT11 void INT_DMAC_DMINT11() { } //;H'920 Reserved void INT_Reserved920() { } //;H'940 Reserved void INT_Reserved940() { } //;H'960 Reserved void INT_Reserved960() { } //;H'980 Reserved void INT_Reserved980() { } //;H'9A0 Reserved void INT_Reserved9A0() { } //;H'9C0 Reserved void INT_Reserved9C0() { } //;H'9E0 Reserved void INT_Reserved9E0() { } //;H'A00 ATU3_TA_ICIA00 void INT_ATU3_TA_ICIA00() { } //;H'A20 ATU3_TA_ICIA01 void INT_ATU3_TA_ICIA01() { } //;H'A40 ATU3_TA_ICIA02 void INT_ATU3_TA_ICIA02() { } //;H'A60 ATU3_TA_ICIA03 void INT_ATU3_TA_ICIA03() { } //;H'A80 ATU3_TA_ICIA04 void INT_ATU3_TA_ICIA04() { } //;H'AA0 ATU3_TA_ICIA05 void INT_ATU3_TA_ICIA05() { } //;H'AC0 ATU3_TA_OVIA0 void INT_ATU3_TA_OVIA0() { } //;H'AE0 Reserved void INT_ReservedAE0() { } //;H'B00 ATU3_TF_ICIF0 void INT_ATU3_TF_ICIF0() { } //;H'B20 ATU3_TF_ICIF1 void INT_ATU3_TF_ICIF1() { } //;H'B40 ATU3_TF_ICIF2 void INT_ATU3_TF_ICIF2() { } //;H'B60 ATU3_TF_ICIF3 void INT_ATU3_TF_ICIF3() { } //;H'B80 ATU3_TF_OVIF0 void INT_ATU3_TF_OVIF0() { } //;H'BA0 ATU3_TF_OVIF1 void INT_ATU3_TF_OVIF1() { } //;H'BC0 ATU3_TF_OVIF2 void INT_ATU3_TF_OVIF2() { } //;H'BE0 ATU3_TF_OVIF3 void INT_ATU3_TF_OVIF3() { } //;H'C00 ATU3_TG_CMIG0 void INT_ATU3_TG_CMIG0() { } //;H'C20 ATU3_TG_CMIG1 void INT_ATU3_TG_CMIG1() { } //;H'C40 ATU3_TG_CMIG2 void INT_ATU3_TG_CMIG2() { } //;H'C60 ATU3_TG_CMIG3 void INT_ATU3_TG_CMIG3() { } //;H'C80 ATU3_TG_CMIG4 void INT_ATU3_TG_CMIG4() { } //;H'CA0 ATU3_TG_CMIG5 void INT_ATU3_TG_CMIG5() { } //;H'CC0 Reserved void INT_ReservedCC0() { } //;H'CE0 Reserved void INT_ReservedCE0() { } //;H'D00 ATU3_TOU_TOU00UDF void INT_ATU3_TOU_TOU00UDF() { } //;H'D20 ATU3_TOU_TOU01UDF void INT_ATU3_TOU_TOU01UDF() { } //;H'D40 ATU3_TOU_TOU02UDF void INT_ATU3_TOU_TOU02UDF() { } //;H'D60 ATU3_TOU_TOU03UDF void INT_ATU3_TOU_TOU03UDF() { } //;H'D80 ATU3_TOU_TOU04UDF void INT_ATU3_TOU_TOU04UDF() { } //;H'DA0 ATU3_TOU_TOU05UDF void INT_ATU3_TOU_TOU05UDF() { } //;H'DC0 ATU3_TOU_TOU06UDF void INT_ATU3_TOU_TOU06UDF() { } //;H'DE0 ATU3_TOU_TOU07UDF void INT_ATU3_TOU_TOU07UDF() { } //;H'E00 ATU3_TOU_TOU10UDF void INT_ATU3_TOU_TOU10UDF() { } //;H'E20 ATU3_TOU_TOU11UDF void INT_ATU3_TOU_TOU11UDF() { } //;H'E40 ATU3_TOU_TOU12UDF void INT_ATU3_TOU_TOU12UDF() { } //;H'E60 ATU3_TOU_TOU13UDF void INT_ATU3_TOU_TOU13UDF() { } //;H'E80 ATU3_TOU_TOU14UDF void INT_ATU3_TOU_TOU14UDF() { } //;H'EA0 ATU3_TOU_TOU15UDF void INT_ATU3_TOU_TOU15UDF() { } //;H'EC0 ATU3_TOU_TOU16UDF void INT_ATU3_TOU_TOU16UDF() { } //;H'EE0 ATU3_TOU_TOU17UDF void INT_ATU3_TOU_TOU17UDF() { } //;H'F00 ATU3_TOU_TOU20UDF void INT_ATU3_TOU_TOU20UDF() { } //;H'F20 ATU3_TOU_TOU21UDF void INT_ATU3_TOU_TOU21UDF() { } //;H'F40 ATU3_TOU_TOU22UDF void INT_ATU3_TOU_TOU22UDF() { } //;H'F60 ATU3_TOU_TOU23UDF void INT_ATU3_TOU_TOU23UDF() { } //;H'F80 ATU3_TOU_TOU24UDF void INT_ATU3_TOU_TOU24UDF() { } //;H'FA0 ATU3_TOU_TOU25UDF void INT_ATU3_TOU_TOU25UDF() { } //;H'FC0 ATU3_TOU_TOU26UDF void INT_ATU3_TOU_TOU26UDF() { } //;H'FE0 ATU3_TOU_TOU27UDF void INT_ATU3_TOU_TOU27UDF() { } //;H'1000 ATU3_TOU_TOU30UDF void INT_ATU3_TOU_TOU30UDF() { } //;H'1020 ATU3_TOU_TOU31UDF void INT_ATU3_TOU_TOU31UDF() { } //;H'1040 ATU3_TOU_TOU32UDF void INT_ATU3_TOU_TOU32UDF() { } //;H'1060 ATU3_TOU_TOU33UDF void INT_ATU3_TOU_TOU33UDF() { } //;H'1080 ATU3_TOU_TOU34UDF void INT_ATU3_TOU_TOU34UDF() { } //;H'10A0 ATU3_TOU_TOU35UDF void INT_ATU3_TOU_TOU35UDF() { } //;H'10C0 ATU3_TOU_TOU36UDF void INT_ATU3_TOU_TOU36UDF() { } //;H'10E0 ATU3_TOU_TOU37UDF void INT_ATU3_TOU_TOU37UDF() { } //;H'1100 ATU3_TOU_TOU40UDF void INT_ATU3_TOU_TOU40UDF() { } //;H'1120 ATU3_TOU_TOU41UDF void INT_ATU3_TOU_TOU41UDF() { } //;H'1140 ATU3_TOU_TOU42UDF void INT_ATU3_TOU_TOU42UDF() { } //;H'1160 ATU3_TOU_TOU43UDF void INT_ATU3_TOU_TOU43UDF() { } //;H'1180 ATU3_TOU_TOU44UDF void INT_ATU3_TOU_TOU44UDF() { } //;H'11A0 ATU3_TOU_TOU45UDF void INT_ATU3_TOU_TOU45UDF() { } //;H'11C0 ATU3_TOU_TOU46UDF void INT_ATU3_TOU_TOU46UDF() { } //;H'11E0 ATU3_TOU_TOU47UDF void INT_ATU3_TOU_TOU47UDF() { } //;H'1200 SCIF_ERI0 void INT_SCIF_ERI0() { } //;H'1220 SCIF_RXI0 void INT_SCIF_RXI0() { } //;H'1240 SCIF_BRI0 void INT_SCIF_BRI0() { } //;H'1260 SCIF_TXI0 void INT_SCIF_TXI0() { } //;H'1280 SCIF_ERI1 void INT_SCIF_ERI1() { } //;H'12A0 SCIF_RXI1 void INT_SCIF_RXI1() { } //;H'12C0 SCIF_BRI1 void INT_SCIF_BRI1() { } //;H'12E0 SCIF_TXI1 void INT_SCIF_TXI1() { } //;H'1300 SCIF_ERI2 void INT_SCIF_ERI2() { } //;H'1320 SCIF_RXI2 void INT_SCIF_RXI2() { } //;H'1340 SCIF_BRI2 void INT_SCIF_BRI2() { } //;H'1360 SCIF_TXI2 void INT_SCIF_TXI2() { } //;H'1380 SCIF_ERI3 void INT_SCIF_ERI3() { } //;H'13A0 SCIF_RXI3 void INT_SCIF_RXI3() { } //;H'13C0 SCIF_BRI3 void INT_SCIF_BRI3() { } //;H'13E0 SCIF_TXI3 void INT_SCIF_TXI3() { } //;H'1400 RSPI_SPEI0 void INT_RSPI_SPEI0() { } //;H'1420 RSPI_SPRI0 void INT_RSPI_SPRI0() { } //;H'1440 RSPI_SPTI0 void INT_RSPI_SPTI0() { } //;H'1460 RSPI_SPEI1 void INT_RSPI_SPEI1() { } //;H'1480 RSPI_SPRI1 void INT_RSPI_SPRI1() { } //;H'14A0 RSPI_SPTI1 void INT_RSPI_SPTI1() { } //;H'14C0 RSPI_SPEI2 void INT_RSPI_SPEI2() { } //;H'14E0 RSPI_SPRI2 void INT_RSPI_SPRI2() { } //;H'1500 RSPI_SPTI2 void INT_RSPI_SPTI2() { } //;H'1520 Reserved void INT_Reserved1520() { } //;H'1540 Reserved void INT_Reserved1540() { } //;H'1560 Reserved void INT_Reserved1560() { } //;H'1580 Reserved void INT_Reserved1580() { } //;H'15A0 Reserved void INT_Reserved15A0() { } //;H'15C0 Reserved void INT_Reserved15C0() { } //;H'15E0 Reserved void INT_Reserved15E0() { } //;H'1600 IIC3_IICI void INT_IIC3_IICI() { } //;H'1620 Reserved void INT_Reserved1620() { } //;H'1640 Reserved void INT_Reserved1640() { } //;H'1660 Reserved void INT_Reserved1660() { } //;H'1680 Reserved void INT_Reserved1680() { } //;H'16A0 Reserved void INT_Reserved16A0() { } //;H'16C0 Reserved void INT_Reserved16C0() { } //;H'16E0 Reserved void INT_Reserved16E0() { } //;H'1700 DRI_DRI0EVENT void INT_DRI_DRI0EVENT() { } //;H'1720 DRI_DRI0DEC void INT_DRI_DRI0DEC() { } //;H'1740 DRI_DRI0TRM void INT_DRI_DRI0TRM() { } //;H'1760 DRI_DRI1EVENT void INT_DRI_DRI1EVENT() { } //;H'1780 DRI_DRI1DEC void INT_DRI_DRI1DEC() { } //;H'17A0 DRI_DRI1TRM void INT_DRI_DRI1TRM() { } //;H'17C0 DRI_DRI2EVENT void INT_DRI_DRI2EVENT() { } //;H'17E0 DRI_DRI2DEC void INT_DRI_DRI2DEC() { } //;H'1800 DRI_DRI2TRM void INT_DRI_DRI2TRM() { } //;H'1820 DRO_DRO void INT_DRO_DRO() { } //;H'1840 Reserved void INT_Reserved1840() { } //;H'1860 Reserved void INT_Reserved1860() { } //;H'1880 Reserved void INT_Reserved1880() { } //;H'18A0 Reserved void INT_Reserved18A0() { } //;H'18C0 Reserved void INT_Reserved18C0() { } //;H'18E0 Reserved void INT_Reserved18E0() { } //;H'1900 FlexRay_FRINT0 void INT_FlexRay_FRINT0() { } //;H'1920 FlexRay_FRINT1 void INT_FlexRay_FRINT1() { } //;H'1940 FlexRay_FRTINT0 void INT_FlexRay_FRTINT0() { } //;H'1960 FlexRay_FRTINT1 void INT_FlexRay_FRTINT1() { } //;H'1980 Reserved void INT_Reserved1980() { } //;H'19A0 Reserved void INT_Reserved19A0() { } //;H'19C0 Reserved void INT_Reserved19C0() { } //;H'19E0 Reserved void INT_Reserved19E0() { } //;H'1A00 CAN_ERS0 void INT_CAN_ERS0() { } //;H'1A20 CAN_RXF0 void INT_CAN_RXF0() { } //;H'1A40 CAN_TXF0 void INT_CAN_TXF0() { } //;H'1A60 Reserved void INT_Reserved1A60() { } //;H'1A80 CAN_RXM00 void INT_CAN_RXM00() { } //;H'1AA0 CAN_RXM10 void INT_CAN_RXM10() { } //;H'1AC0 CAN_TXM0 void INT_CAN_TXM0() { } //;H'1AE0 Reserved void INT_Reserved1AE0() { } //;H'1B00 CAN_ERS1 void INT_CAN_ERS1() { } //;H'1B20 CAN_RXF1 void INT_CAN_RXF1() { } //;H'1B40 CAN_TXF1 void INT_CAN_TXF1() { } //;H'1B60 Reserved void INT_Reserved1B60() { } //;H'1B80 CAN_RXM01 void INT_CAN_RXM01() { } //;H'1BA0 CAN_RXM11 void INT_CAN_RXM11() { } //;H'1BC0 CAN_TXM1 void INT_CAN_TXM1() { } //;H'1BE0 Reserved void INT_Reserved1BE0() { } //;H'1C00 CAN_ERS2 void INT_CAN_ERS2() { } //;H'1C20 CAN_RXF2 void INT_CAN_RXF2() { } //;H'1C40 CAN_TXF2 void INT_CAN_TXF2() { } //;H'1C60 Reserved void INT_Reserved1C60() { } //;H'1C80 CAN_RXM02 void INT_CAN_RXM02() { } //;H'1CA0 CAN_RXM12 void INT_CAN_RXM12() { } //;H'1CC0 CAN_TXM2 void INT_CAN_TXM2() { } //;H'1CE0 Reserved void INT_Reserved1CE0() { } //;H'1D00 CAN_ERS3 void INT_CAN_ERS3() { } //;H'1D20 CAN_RXF3 void INT_CAN_RXF3() { } //;H'1D40 CAN_TXF3 void INT_CAN_TXF3() { } //;H'1D60 Reserved void INT_Reserved1D60() { } //;H'1D80 CAN_RXM03 void INT_CAN_RXM03() { } //;H'1DA0 CAN_RXM13 void INT_CAN_RXM13() { } //;H'1DC0 CAN_TXM3 void INT_CAN_TXM3() { } //;H'1EE0 Reserved void INT_Reserved1EE0() { } //;H'1E00 ADC_AD0I void INT_ADC_AD0I() { } //;H'1E20 ADC_AD1I void INT_ADC_AD1I() { } //;H'1E40 ADC_AD0ID0 void INT_ADC_AD0ID0() { } //;H'1E60 ADC_AD0ID1 void INT_ADC_AD0ID1() { } //;H'1E80 ADC_AD0ID2 void INT_ADC_AD0ID2() { } //;H'1EA0 ADC_AD0ID3 void INT_ADC_AD0ID3() { } //;H'1EC0 ADC_AD0ID4 void INT_ADC_AD0ID4() { } //;H'1EE0 ADC_AD0ID5 void INT_ADC_AD0ID5() { } //;H'1F00 ADC_AD0ID6 void INT_ADC_AD0ID6() { } //;H'1F20 ADC_AD0ID7 void INT_ADC_AD0ID7() { } //;H'1F40 ADC_AD0ID8 void INT_ADC_AD0ID8() { } //;H'1F60 ADC_AD0ID9 void INT_ADC_AD0ID9() { } //;H'1F80 ADC_AD0ID10 void INT_ADC_AD0ID10() { } //;H'1FA0 ADC_AD0ID11 void INT_ADC_AD0ID11() { } //;H'1FC0 ADC_AD0ID12 void INT_ADC_AD0ID12() { } //;H'1FE0 ADC_AD0ID13 void INT_ADC_AD0ID13() { } //;H'2000 ADC_AD0ID14 void INT_ADC_AD0ID14() { } //;H'2020 ADC_AD0ID15 void INT_ADC_AD0ID15() { } //;H'2040 ADC_AD1ID0 void INT_ADC_AD1ID0() { } //;H'2060 ADC_AD1ID1 void INT_ADC_AD1ID1() { } //;H'2080 ADC_AD1ID2 void INT_ADC_AD1ID2() { } //;H'20A0 ADC_AD1ID3 void INT_ADC_AD1ID3() { } //;H'20C0 ADC_AD1ID4 void INT_ADC_AD1ID4() { } //;H'20E0 ADC_AD1ID5 void INT_ADC_AD1ID5() { } //;H'2100 ADC_AD1ID6 void INT_ADC_AD1ID6() { } //;H'2120 ADC_AD1ID7 void INT_ADC_AD1ID7() { } //;H'2140 Reserved void INT_Reserved2140() { } //;H'2160 Reserved void INT_Reserved2160() { } //;H'2180 Reserved void INT_Reserved2180() { } //;H'21A0 Reserved void INT_Reserved21A0() { } //;H'21C0 Reserved void INT_Reserved21C0() { } //;H'21E0 Reserved void INT_Reserved21E0() { } //;H'2200 PDAC_PDIINT void INT_PDAC_PDIINT() { } //;H'2220 Reserved void INT_Reserved2220() { } //;H'2240 Reserved void INT_Reserved2240() { } //;H'2260 Reserved void INT_Reserved2260() { } //;H'2280 Reserved void INT_Reserved2280() { } //;H'22A0 Reserved void INT_Reserved22A0() { } //;H'22C0 Reserved void INT_Reserved22C0() { } //;H'22E0 Reserved void INT_Reserved22E0() { } //;H'2300 ATU3_TA_ICIA10 void INT_ATU3_TA_ICIA10() { } //;H'2320 ATU3_TA_ICIA11 void INT_ATU3_TA_ICIA11() { } //;H'2340 ATU3_TA_ICIA12 void INT_ATU3_TA_ICIA12() { } //;H'2360 ATU3_TA_ICIA13 void INT_ATU3_TA_ICIA13() { } //;H'2380 ATU3_TA_ICIA14 void INT_ATU3_TA_ICIA14() { } //;H'23A0 ATU3_TA_ICIA15 void INT_ATU3_TA_ICIA15() { } //;H'23C0 ATU3_TA_OVIA1 void INT_ATU3_TA_OVIA1() { } //;H'23E0 Reserved void INT_Reserved23E0() { } //;H'2400 CAN_ERS4 void INT_CAN_ERS4() { } //;H'2420 CAN_RXF4 void INT_CAN_RXF4() { } //;H'2440 CAN_TXF4 void INT_CAN_TXF4() { } //;H'2460 Reserved void INT_Reserved2460() { } //;H'2480 CAN_RXM04 void INT_CAN_RXM04() { } //;H'24A0 CAN_RXM14 void INT_CAN_RXM14() { } //;H'24C0 CAN_TXM4 void INT_CAN_TXM4() { }

　Renesas のものと同じ（省略）

　PG1.2 V2.0A //<<VECTOR DATA START (POWER ON RESET)>> //;H'000 Power On Reset (Hitachi-UDI RESET) //<<VECTOR DATA END (POWER ON RESET)>> //;H'020 Reserved void INT_Reserved020(void); //;H'040 Data TLB miss exception(read) void INT_TLB_MISS_READ_EXP(void); //;H'060 Data TLB miss exception(write) void INT_TLB_MISS_WRITE_EXP(void); //;H'080 Initial page write exception void INT_TLB_INIT_PAGE_EXP(void); //;H'0A0 Data TLB protection violation exception (read) void INT_TLB_PROTECT_READ_EXP(void); //;H'0C0 Data TLB protection violation exception (write) void INT_TLB_PROTECT_WRITE_EXP(void); //;H'0E0 Data address error(read) void INT_ADR_ERROR_READ(void); //;H'100 Data address error(write) void INT_ADR_ERROR_WRITE(void); //;H'120 FPU exception void INT_FPU_EXP(void); //;H'140 Reserved void INT_Reserved140(void); //;H'160 Unconditional trap(TRAPA) void INT_TRAP(void); //;H'180 General illegal instruction exception void INT_ILLEGAL_INST_EXP(void); //;H'1A0 Slot illegal instruction exception void INT_ILLEGAL_SLOT_EXP(void); //;H'1C0 NMI void INT_NMI(void); //;H'1E0 USER_BREAK void INT_USER_BREAK(void); //;H'200 IRQ IRQ7 void INT_IRQ7(void); //;H'220 Reserved void INT_Reserved220(void); //;H'240 IRQ IRQ0 void INT_IRQ0(void); //;H'260 Reserved void INT_Reserved260(void); //;H'280 IRQ IRQ1 void INT_IRQ1(void); //;H'2A0 Reserved void INT_Reserved2A0(void); //;H'2C0 IRQ IRQ2 void INT_IRQ2(void); //;H'2E0 Reserved void INT_Reserved2E0(void); //;H'300 IRQ IRQ3 void INT_IRQ3(void); //;H'320 Reserved void INT_Reserved320(void); //;H'340 IRQ IRQ4 void INT_IRQ4(void); //;H'360 Reserved void INT_Reserved360(void); //;H'380 IRQ IRQ5 void INT_IRQ5(void); //;H'3A0 Reserved void INT_Reserved3A0(void); //;H'3C0 IRQ IRQ6 void INT_IRQ6(void); //;H'3E0 Reserved void INT_Reserved3E0(void); //;H'400 Reserved void INT_Reserved400(void); //;H'420 Reserved void INT_Reserved420(void); //;H'440 Reserved void INT_Reserved440(void); //;H'460 Reserved void INT_Reserved460(void); //;H'480 Reserved void INT_Reserved480(void); //;H'4A0 Reserved void INT_Reserved4A0(void); //;H'4C0 Reserved void INT_Reserved4C0(void); //;H'4E0 Reserved void INT_Reserved4E0(void); //;H'500 Reserved void INT_Reserved500(void); //;H'520 Reserved void INT_Reserved520(void); //;H'540 Reserved void INT_Reserved540(void); //;H'560 WDT ITI void INT_WDT_ITI(void); //;H'580 TMU0 void INT_TMU0_TUNI0(void); //;H'5A0 TMU1 void INT_TMU1_TUNI1(void); //;H'5C0 TMU2 underflow interrupt void INT_TMU2_TUNI2(void); //;H'5E0 Reserved void INT_Reserved5E0(void); //;H'600 H-UDI interrupt void INT_H_UDI(void); //;H'620 Reserved void INT_Reserved620(void); //;H'640 Reserved void INT_Reserved640(void); //;H'660 Reserved void INT_Reserved660(void); //;H'680 Reserved void INT_Reserved680(void); //;H'6A0 Reserved void INT_Reserved6A0(void); //;H'6C0 Reserved void INT_Reserved6C0(void); //;H'6E0 Reserved void INT_Reserved6E0(void); //;H'700 DMAC_DMINT0 void INT_DMAC_DMINT0(void); //;H'720 DMAC_DMINT1 void INT_DMAC_DMINT1(void); //;H'740 DMAC_DMINT2 void INT_DMAC_DMINT2(void); //;H'760 DMAC_DMINT3 void INT_DMAC_DMINT3(void); //;H'780 DMAC_DMAE0 void INT_DMAC_DMAE0(void); //;H'7A0 DMAC_DMAE1 void INT_DMAC_DMAE1(void); //;H'7C0 DMAC_DMINT4 void INT_DMAC_DMINT4(void); //;H'7E0 Reserved void INT_Reserved7E0(void); //;H'800 General fpu disable exception void INT_FPU_DISABLE_EXP(void); //;H'820 Slot fpu disable exception void INT_FPU_SLOT_DISABLE_EXP(void); //;H'840 DMAC_DMINT5 void INT_DMAC_DMINT5(void); //;H'860 DMAC_DMINT6 void INT_DMAC_DMINT6(void); //;H'880 DMAC_DMINT7 void INT_DMAC_DMINT7(void); //;H'8A0 DMAC_DMINT8 void INT_DMAC_DMINT8(void); //;H'8C0 DMAC_DMINT9 void INT_DMAC_DMINT9(void); //;H'8E0 DMAC_DMINT10 void INT_DMAC_DMINT10(void); //;H'900 DMAC_DMINT11 void INT_DMAC_DMINT11(void); //;H'920 Reserved void INT_Reserved920(void); //;H'940 Reserved void INT_Reserved940(void); //;H'960 Reserved void INT_Reserved960(void); //;H'980 Reserved void INT_Reserved980(void); //;H'9A0 Reserved void INT_Reserved9A0(void); //;H'9C0 Reserved void INT_Reserved9C0(void); //;H'9E0 Reserved void INT_Reserved9E0(void); //;H'A00 ATU3_TA_ICIA00 void INT_ATU3_TA_ICIA00(void); //;H'A20 ATU3_TA_ICIA01 void INT_ATU3_TA_ICIA01(void); //;H'A40 ATU3_TA_ICIA02 void INT_ATU3_TA_ICIA02(void); //;H'A60 ATU3_TA_ICIA03 void INT_ATU3_TA_ICIA03(void); //;H'A80 ATU3_TA_ICIA04 void INT_ATU3_TA_ICIA04(void); //;H'AA0 ATU3_TA_ICIA05 void INT_ATU3_TA_ICIA05(void); //;H'AC0 ATU3_TA_OVIA0 void INT_ATU3_TA_OVIA0(void); //;H'AE0 Reserved void INT_ReservedAE0(void); //;H'B00 ATU3_TF_ICIF0 void INT_ATU3_TF_ICIF0(void); //;H'B20 ATU3_TF_ICIF1 void INT_ATU3_TF_ICIF1(void); //;H'B40 ATU3_TF_ICIF2 void INT_ATU3_TF_ICIF2(void); //;H'B60 ATU3_TF_ICIF3 void INT_ATU3_TF_ICIF3(void); //;H'B80 ATU3_TF_OVIF0 void INT_ATU3_TF_OVIF0(void); //;H'BA0 ATU3_TF_OVIF1 void INT_ATU3_TF_OVIF1(void); //;H'BC0 ATU3_TF_OVIF2 void INT_ATU3_TF_OVIF2(void); //;H'BE0 ATU3_TF_OVIF3 void INT_ATU3_TF_OVIF3(void); //;H'C00 ATU3_TG_CMIG0 void INT_ATU3_TG_CMIG0(void); //;H'C20 ATU3_TG_CMIG1 void INT_ATU3_TG_CMIG1(void); //;H'C40 ATU3_TG_CMIG2 void INT_ATU3_TG_CMIG2(void); //;H'C60 ATU3_TG_CMIG3 void INT_ATU3_TG_CMIG3(void); //;H'C80 ATU3_TG_CMIG4 void INT_ATU3_TG_CMIG4(void); //;H'CA0 ATU3_TG_CMIG5 void INT_ATU3_TG_CMIG5(void); //;H'CC0 Reserved void INT_ReservedCC0(void); //;H'CE0 Reserved void INT_ReservedCE0(void); //;H'D00 ATU3_TOU_TOU00UDF void INT_ATU3_TOU_TOU00UDF(void); //;H'D20 ATU3_TOU_TOU01UDF void INT_ATU3_TOU_TOU01UDF(void); //;H'D40 ATU3_TOU_TOU02UDF void INT_ATU3_TOU_TOU02UDF(void); //;H'D60 ATU3_TOU_TOU03UDF void INT_ATU3_TOU_TOU03UDF(void); //;H'D80 ATU3_TOU_TOU04UDF void INT_ATU3_TOU_TOU04UDF(void); //;H'DA0 ATU3_TOU_TOU05UDF void INT_ATU3_TOU_TOU05UDF(void); //;H'DC0 ATU3_TOU_TOU06UDF void INT_ATU3_TOU_TOU06UDF(void); //;H'DE0 ATU3_TOU_TOU07UDF void INT_ATU3_TOU_TOU07UDF(void); //;H'E00 ATU3_TOU_TOU10UDF void INT_ATU3_TOU_TOU10UDF(void); //;H'E20 ATU3_TOU_TOU11UDF void INT_ATU3_TOU_TOU11UDF(void); //;H'E40 ATU3_TOU_TOU12UDF void INT_ATU3_TOU_TOU12UDF(void); //;H'E60 ATU3_TOU_TOU13UDF void INT_ATU3_TOU_TOU13UDF(void); //;H'E80 ATU3_TOU_TOU14UDF void INT_ATU3_TOU_TOU14UDF(void); //;H'EA0 ATU3_TOU_TOU15UDF void INT_ATU3_TOU_TOU15UDF(void); //;H'EC0 ATU3_TOU_TOU16UDF void INT_ATU3_TOU_TOU16UDF(void); //;H'EE0 ATU3_TOU_TOU17UDF void INT_ATU3_TOU_TOU17UDF(void); //;H'F00 ATU3_TOU_TOU20UDF void INT_ATU3_TOU_TOU20UDF(void); //;H'F20 ATU3_TOU_TOU21UDF void INT_ATU3_TOU_TOU21UDF(void); //;H'F40 ATU3_TOU_TOU22UDF void INT_ATU3_TOU_TOU22UDF(void); //;H'F60 ATU3_TOU_TOU23UDF void INT_ATU3_TOU_TOU23UDF(void); //;H'F80 ATU3_TOU_TOU24UDF void INT_ATU3_TOU_TOU24UDF(void); //;H'FA0 ATU3_TOU_TOU25UDF void INT_ATU3_TOU_TOU25UDF(void); //;H'FC0 ATU3_TOU_TOU26UDF void INT_ATU3_TOU_TOU26UDF(void); //;H'FE0 ATU3_TOU_TOU27UDF void INT_ATU3_TOU_TOU27UDF(void); //;H'1000 ATU3_TOU_TOU30UDF void INT_ATU3_TOU_TOU30UDF(void); //;H'1020 ATU3_TOU_TOU31UDF void INT_ATU3_TOU_TOU31UDF(void); //;H'1040 ATU3_TOU_TOU32UDF void INT_ATU3_TOU_TOU32UDF(void); //;H'1060 ATU3_TOU_TOU33UDF void INT_ATU3_TOU_TOU33UDF(void); //;H'1080 ATU3_TOU_TOU34UDF void INT_ATU3_TOU_TOU34UDF(void); //;H'10A0 ATU3_TOU_TOU35UDF void INT_ATU3_TOU_TOU35UDF(void); //;H'10C0 ATU3_TOU_TOU36UDF void INT_ATU3_TOU_TOU36UDF(void); //;H'10E0 ATU3_TOU_TOU37UDF void INT_ATU3_TOU_TOU37UDF(void); //;H'1100 ATU3_TOU_TOU40UDF void INT_ATU3_TOU_TOU40UDF(void); //;H'1120 ATU3_TOU_TOU41UDF void INT_ATU3_TOU_TOU41UDF(void); //;H'1140 ATU3_TOU_TOU42UDF void INT_ATU3_TOU_TOU42UDF(void); //;H'1160 ATU3_TOU_TOU43UDF void INT_ATU3_TOU_TOU43UDF(void); //;H'1180 ATU3_TOU_TOU44UDF void INT_ATU3_TOU_TOU44UDF(void); //;H'11A0 ATU3_TOU_TOU45UDF void INT_ATU3_TOU_TOU45UDF(void); //;H'11C0 ATU3_TOU_TOU46UDF void INT_ATU3_TOU_TOU46UDF(void); //;H'11E0 ATU3_TOU_TOU47UDF void INT_ATU3_TOU_TOU47UDF(void); //;H'1200 SCIF_ERI0 void INT_SCIF_ERI0(void); //;H'1220 SCIF_RXI0 void INT_SCIF_RXI0(void); //;H'1240 SCIF_BRI0 void INT_SCIF_BRI0(void); //;H'1260 SCIF_TXI0 void INT_SCIF_TXI0(void); //;H'1280 SCIF_ERI1 void INT_SCIF_ERI1(void); //;H'12A0 SCIF_RXI1 void INT_SCIF_RXI1(void); //;H'12C0 SCIF_BRI1 void INT_SCIF_BRI1(void); //;H'12E0 SCIF_TXI1 void INT_SCIF_TXI1(void); //;H'1300 SCIF_ERI2 void INT_SCIF_ERI2(void); //;H'1320 SCIF_RXI2 void INT_SCIF_RXI2(void); //;H'1340 SCIF_BRI2 void INT_SCIF_BRI2(void); //;H'1360 SCIF_TXI2 void INT_SCIF_TXI2(void); //;H'1380 SCIF_ERI3 void INT_SCIF_ERI3(void); //;H'13A0 SCIF_RXI3 void INT_SCIF_RXI3(void); //;H'13C0 SCIF_BRI3 void INT_SCIF_BRI3(void); //;H'13E0 SCIF_TXI3 void INT_SCIF_TXI3(void); //;H'1400 RSPI_SPEI0 void INT_RSPI_SPEI0(void); //;H'1420 RSPI_SPRI0 void INT_RSPI_SPRI0(void); //;H'1440 RSPI_SPTI0 void INT_RSPI_SPTI0(void); //;H'1460 RSPI_SPEI1 void INT_RSPI_SPEI1(void); //;H'1480 RSPI_SPRI1 void INT_RSPI_SPRI1(void); //;H'14A0 RSPI_SPTI1 void INT_RSPI_SPTI1(void); //;H'14C0 RSPI_SPEI2 void INT_RSPI_SPEI2(void); //;H'14E0 RSPI_SPRI2 void INT_RSPI_SPRI2(void); //;H'1500 RSPI_SPTI2 void INT_RSPI_SPTI2(void); //;H'1520 Reserved void INT_Reserved1520(void); //;H'1540 Reserved void INT_Reserved1540(void); //;H'1560 Reserved void INT_Reserved1560(void); //;H'1580 Reserved void INT_Reserved1580(void); //;H'15A0 Reserved void INT_Reserved15A0(void); //;H'15C0 Reserved void INT_Reserved15C0(void); //;H'15E0 Reserved void INT_Reserved15E0(void); //;H'1600 IIC3_IICI void INT_IIC3_IICI(void); //;H'1620 Reserved void INT_Reserved1620(void); //;H'1640 Reserved void INT_Reserved1640(void); //;H'1660 Reserved void INT_Reserved1660(void); //;H'1680 Reserved void INT_Reserved1680(void); //;H'16A0 Reserved void INT_Reserved16A0(void); //;H'16C0 Reserved void INT_Reserved16C0(void); //;H'16E0 Reserved void INT_Reserved16E0(void); //;H'1700 DRI_DRI0EVENT void INT_DRI_DRI0EVENT(void); //;H'1720 DRI_DRI0DEC void INT_DRI_DRI0DEC(void); //;H'1740 DRI_DRI0TRM void INT_DRI_DRI0TRM(void); //;H'1760 DRI_DRI1EVENT void INT_DRI_DRI1EVENT(void); //;H'1780 DRI_DRI1DEC void INT_DRI_DRI1DEC(void); //;H'17A0 DRI_DRI1TRM void INT_DRI_DRI1TRM(void); //;H'17C0 DRI_DRI2EVENT void INT_DRI_DRI2EVENT(void); //;H'17E0 DRI_DRI2DEC void INT_DRI_DRI2DEC(void); //;H'1800 DRI_DRI2TRM void INT_DRI_DRI2TRM(void); //;H'1820 DRO_DRO void INT_DRO_DRO(void); //;H'1840 Reserved void INT_Reserved1840(void); //;H'1860 Reserved void INT_Reserved1860(void); //;H'1880 Reserved void INT_Reserved1880(void); //;H'18A0 Reserved void INT_Reserved18A0(void); //;H'18C0 Reserved void INT_Reserved18C0(void); //;H'18E0 Reserved void INT_Reserved18E0(void); //;H'1900 FlexRay_FRINT0 void INT_FlexRay_FRINT0(void); //;H'1920 FlexRay_FRINT1 void INT_FlexRay_FRINT1(void); //;H'1940 FlexRay_FRTINT0 void INT_FlexRay_FRTINT0(void); //;H'1960 FlexRay_FRTINT1 void INT_FlexRay_FRTINT1(void); //;H'1980 Reserved void INT_Reserved1980(void); //;H'19A0 Reserved void INT_Reserved19A0(void); //;H'19C0 Reserved void INT_Reserved19C0(void); //;H'19E0 Reserved void INT_Reserved19E0(void); //;H'1A00 CAN_ERS0 void INT_CAN_ERS0(void); //;H'1A20 CAN_RXF0 void INT_CAN_RXF0(void); //;H'1A40 CAN_TXF0 void INT_CAN_TXF0(void); //;H'1A60 Reserved void INT_Reserved1A60(void); //;H'1A80 CAN_RXM00 void INT_CAN_RXM00(void); //;H'1AA0 CAN_RXM10 void INT_CAN_RXM10(void); //;H'1AC0 CAN_TXM0 void INT_CAN_TXM0(void); //;H'1AE0 Reserved void INT_Reserved1AE0(void); //;H'1B00 CAN_ERS1 void INT_CAN_ERS1(void); //;H'1B20 CAN_RXF1 void INT_CAN_RXF1(void); //;H'1B40 CAN_TXF1 void INT_CAN_TXF1(void); //;H'1B60 Reserved void INT_Reserved1B60(void); //;H'1B80 CAN_RXM01 void INT_CAN_RXM01(void); //;H'1BA0 CAN_RXM11 void INT_CAN_RXM11(void); //;H'1BC0 CAN_TXM1 void INT_CAN_TXM1(void); //;H'1BE0 Reserved void INT_Reserved1BE0(void); //;H'1C00 CAN_ERS2 void INT_CAN_ERS2(void); //;H'1C20 CAN_RXF2 void INT_CAN_RXF2(void); //;H'1C40 CAN_TXF2 void INT_CAN_TXF2(void); //;H'1C60 Reserved void INT_Reserved1C60(void); //;H'1C80 CAN_RXM02 void INT_CAN_RXM02(void); //;H'1CA0 CAN_RXM12 void INT_CAN_RXM12(void); //;H'1CC0 CAN_TXM2 void INT_CAN_TXM2(void); //;H'1CE0 Reserved void INT_Reserved1CE0(void); //;H'1D00 CAN_ERS3 void INT_CAN_ERS3(void); //;H'1D20 CAN_RXF3 void INT_CAN_RXF3(void); //;H'1D40 CAN_TXF3 void INT_CAN_TXF3(void); //;H'1D60 Reserved void INT_Reserved1D60(void); //;H'1D80 CAN_RXM03 void INT_CAN_RXM03(void); //;H'1DA0 CAN_RXM13 void INT_CAN_RXM13(void); //;H'1DC0 CAN_TXM3 void INT_CAN_TXM3(void); //;H'1EE0 Reserved void INT_Reserved1EE0(void); //;H'1E00 ADC_AD0I void INT_ADC_AD0I(void); //;H'1E20 ADC_AD1I void INT_ADC_AD1I(void); //;H'1E40 ADC_AD0ID0 void INT_ADC_AD0ID0(void); //;H'1E60 ADC_AD0ID1 void INT_ADC_AD0ID1(void); //;H'1E80 ADC_AD0ID2 void INT_ADC_AD0ID2(void); //;H'1EA0 ADC_AD0ID3 void INT_ADC_AD0ID3(void); //;H'1EC0 ADC_AD0ID4 void INT_ADC_AD0ID4(void); //;H'1EE0 ADC_AD0ID5 void INT_ADC_AD0ID5(void); //;H'1F00 ADC_AD0ID6 void INT_ADC_AD0ID6(void); //;H'1F20 ADC_AD0ID7 void INT_ADC_AD0ID7(void); //;H'1F40 ADC_AD0ID8 void INT_ADC_AD0ID8(void); //;H'1F60 ADC_AD0ID9 void INT_ADC_AD0ID9(void); //;H'1F80 ADC_AD0ID10 void INT_ADC_AD0ID10(void); //;H'1FA0 ADC_AD0ID11 void INT_ADC_AD0ID11(void); //;H'1FC0 ADC_AD0ID12 void INT_ADC_AD0ID12(void); //;H'1FE0 ADC_AD0ID13 void INT_ADC_AD0ID13(void); //;H'2000 ADC_AD0ID14 void INT_ADC_AD0ID14(void); //;H'2020 ADC_AD0ID15 void INT_ADC_AD0ID15(void); //;H'2040 ADC_AD1ID0 void INT_ADC_AD1ID0(void); //;H'2060 ADC_AD1ID1 void INT_ADC_AD1ID1(void); //;H'2080 ADC_AD1ID2 void INT_ADC_AD1ID2(void); //;H'20A0 ADC_AD1ID3 void INT_ADC_AD1ID3(void); //;H'20C0 ADC_AD1ID4 void INT_ADC_AD1ID4(void); //;H'20E0 ADC_AD1ID5 void INT_ADC_AD1ID5(void); //;H'2100 ADC_AD1ID6 void INT_ADC_AD1ID6(void); //;H'2120 ADC_AD1ID7 void INT_ADC_AD1ID7(void); //;H'2140 Reserved void INT_Reserved2140(void); //;H'2160 Reserved void INT_Reserved2160(void); //;H'2180 Reserved void INT_Reserved2180(void); //;H'21A0 Reserved void INT_Reserved21A0(void); //;H'21C0 Reserved void INT_Reserved21C0(void); //;H'21E0 Reserved void INT_Reserved21E0(void); //;H'2200 PDAC_PDIINT void INT_PDAC_PDIINT(void); //;H'2220 Reserved void INT_Reserved2220(void); //;H'2240 Reserved void INT_Reserved2240(void); //;H'2260 Reserved void INT_Reserved2260(void); //;H'2280 Reserved void INT_Reserved2280(void); //;H'22A0 Reserved void INT_Reserved22A0(void); //;H'22C0 Reserved void INT_Reserved22C0(void); //;H'22E0 Reserved void INT_Reserved22E0(void); //;H'2300 ATU3_TA_ICIA10 void INT_ATU3_TA_ICIA10(void); //;H'2320 ATU3_TA_ICIA11 void INT_ATU3_TA_ICIA11(void); //;H'2340 ATU3_TA_ICIA12 void INT_ATU3_TA_ICIA12(void); //;H'2360 ATU3_TA_ICIA13 void INT_ATU3_TA_ICIA13(void); //;H'2380 ATU3_TA_ICIA14 void INT_ATU3_TA_ICIA14(void); //;H'23A0 ATU3_TA_ICIA15 void INT_ATU3_TA_ICIA15(void); //;H'23C0 ATU3_TA_OVIA1 void INT_ATU3_TA_OVIA1(void); //;H'23E0 Reserved void INT_Reserved23E0(void); //;H'2400 CAN_ERS4 void INT_CAN_ERS4(void); //;H'2420 CAN_RXF4 void INT_CAN_RXF4(void); //;H'2440 CAN_TXF4 void INT_CAN_TXF4(void); //;H'2460 Reserved void INT_Reserved2460(void); //;H'2480 CAN_RXM04 void INT_CAN_RXM04(void); //;H'24A0 CAN_RXM14 void INT_CAN_RXM14(void); //;H'24C0 CAN_TXM4 void INT_CAN_TXM4(void);

　PG1.2 V2.0A #include "interrupt_handlers.h" extern void start (void); /* Startup code (in start.s) */ /**---------------------------------- ** Typedef for the function pointer **-----------------------------------*/ typedef void (*fp) (void); const void *Exp_Vectors[] = { //;<<VECTOR DATA START (POWER ON RESET)>> //;H'000 Power On Reset PC start, //;<<VECTOR DATA END (POWER ON RESET)>> //;H'020 Reserved INT_Reserved020, //;H'040 Data TLB miss exception(read) INT_TLB_MISS_READ_EXP, //;H'060 Data TLB miss exception(write) INT_TLB_MISS_WRITE_EXP, //;H'080 Initial page write exception INT_TLB_INIT_PAGE_EXP, //;H'0A0 Data TLB protection violation exception (read) INT_TLB_PROTECT_READ_EXP, //;H'0C0 Data TLB protection violation exception (write) INT_TLB_PROTECT_WRITE_EXP, //;H'0E0 Data address error(read) INT_ADR_ERROR_READ, //;H'100 Data address error(write) INT_ADR_ERROR_WRITE, //;H'120 FPU exception INT_FPU_EXP, //;H'140 Reserved INT_Reserved140, //;H'160 Unconditional trap(TRAPA) INT_TRAP, //;H'180 General illegal instruction exception INT_ILLEGAL_INST_EXP, //;H'1A0 Slot illegal instruction exception INT_ILLEGAL_SLOT_EXP, //;EXTERNAL INTERRUPT //;H'1C0 NMI INT_NMI, //;H'1E0 USER_BREAK INT_USER_BREAK, //;H'200 IRQ IRQ7 INT_IRQ7, //;H'220 Reserved INT_Reserved220, //;H'240 IRQ IRQ0 INT_IRQ0, //;H'260 Reserved INT_Reserved260, //;H'280 IRQ IRQ1 INT_IRQ1, //;H'2A0 Reserved INT_Reserved2A0, //;H'2C0 IRQ IRQ2 INT_IRQ2, //;H'2E0 Reserved INT_Reserved2E0, //;H'300 IRQ IRQ3 INT_IRQ3, //;H'320 Reserved INT_Reserved320, //;H'340 IRQ IRQ4 INT_IRQ4, //;H'360 Reserved INT_Reserved360, //;H'380 IRQ IRQ5 INT_IRQ5, //;H'3A0 Reserved INT_Reserved3A0, //;H'3C0 IRQ IRQ6 INT_IRQ6, //;H'3E0 Reserved INT_Reserved3E0, //;H'400 Reserved INT_Reserved400, //;H'420 Reserved INT_Reserved420, //;H'440 Reserved INT_Reserved440, //;H'460 Reserved INT_Reserved460, //;H'480 Reserved INT_Reserved480, //;H'4A0 Reserved INT_Reserved4A0, //;H'4C0 Reserved INT_Reserved4C0, //;H'4E0 Reserved INT_Reserved4E0, //;H'500 Reserved INT_Reserved500, //;H'520 Reserved INT_Reserved520, //;H'540 Reserved INT_Reserved540, //;H'560 WDT ITI INT_WDT_ITI, //;H'580 TMU0 INT_TMU0_TUNI0, //;H'5A0 TMU1 INT_TMU1_TUNI1, //;H'5C0 TMU2 underflow interrupt INT_TMU2_TUNI2, //;H'5E0 Reserved INT_Reserved5E0, //;H'600 H-UDI interrupt INT_H_UDI, //;H'620 Reserved INT_Reserved620, //;H'640 Reserved INT_Reserved640, //;H'660 Reserved INT_Reserved660, //;H'680 Reserved INT_Reserved680, //;H'6A0 Reserved INT_Reserved6A0, //;H'6C0 Reserved INT_Reserved6C0, //;H'6E0 Reserved INT_Reserved6E0, //;H'700 DMAC_DMINT0 INT_DMAC_DMINT0, //;H'720 DMAC_DMINT1 INT_DMAC_DMINT1, //;H'740 DMAC_DMINT2 INT_DMAC_DMINT2, //;H'760 DMAC_DMINT3 INT_DMAC_DMINT3, //;H'780 DMAC_DMAE0 INT_DMAC_DMAE0, //;H'7A0 DMAC_DMAE1 INT_DMAC_DMAE1, //;H'7C0 DMAC_DMINT4 INT_DMAC_DMINT4, //;H'7E0 Reserved INT_Reserved7E0, //;H'800 General fpu disable exception INT_FPU_DISABLE_EXP, //;H'820 Slot fpu disable exception INT_FPU_SLOT_DISABLE_EXP, //;H'840 DMAC_DMINT5 INT_DMAC_DMINT5, //;H'860 DMAC_DMINT6 INT_DMAC_DMINT6, //;H'880 DMAC_DMINT7 INT_DMAC_DMINT7, //;H'8A0 DMAC_DMINT8 INT_DMAC_DMINT8, //;H'8C0 DMAC_DMINT9 INT_DMAC_DMINT9, //;H'8E0 DMAC_DMINT10 INT_DMAC_DMINT10, //;H'900 DMAC_DMINT11 INT_DMAC_DMINT11, //;H'920 Reserved INT_Reserved920, //;H'940 Reserved INT_Reserved940, //;H'960 Reserved INT_Reserved960, //;H'980 Reserved INT_Reserved980, //;H'9A0 Reserved INT_Reserved9A0, //;H'9C0 Reserved INT_Reserved9C0, //;H'9E0 Reserved INT_Reserved9E0, //;H'A00 ATU3_TA_ICIA00 INT_ATU3_TA_ICIA00, //;H'A20 ATU3_TA_ICIA01 INT_ATU3_TA_ICIA01, //;H'A40 ATU3_TA_ICIA02 INT_ATU3_TA_ICIA02, //;H'A60 ATU3_TA_ICIA03 INT_ATU3_TA_ICIA03, //;H'A80 ATU3_TA_ICIA04 INT_ATU3_TA_ICIA04, //;H'AA0 ATU3_TA_ICIA05 INT_ATU3_TA_ICIA05, //;H'AC0 ATU3_TA_OVIA0 INT_ATU3_TA_OVIA0, //;H'AE0 Reserved INT_ReservedAE0, //;H'B00 ATU3_TF_ICIF0 INT_ATU3_TF_ICIF0, //;H'B20 ATU3_TF_ICIF1 INT_ATU3_TF_ICIF1, //;H'B40 ATU3_TF_ICIF2 INT_ATU3_TF_ICIF2, //;H'B60 ATU3_TF_ICIF3 INT_ATU3_TF_ICIF3, //;H'B80 ATU3_TF_OVIF0 INT_ATU3_TF_OVIF0, //;H'BA0 ATU3_TF_OVIF1 INT_ATU3_TF_OVIF1, //;H'BC0 ATU3_TF_OVIF2 INT_ATU3_TF_OVIF2, //;H'BE0 ATU3_TF_OVIF3 INT_ATU3_TF_OVIF3, //;H'C00 ATU3_TG_CMIG0 INT_ATU3_TG_CMIG0, //;H'C20 ATU3_TG_CMIG1 INT_ATU3_TG_CMIG1, //;H'C40 ATU3_TG_CMIG2 INT_ATU3_TG_CMIG2, //;H'C60 ATU3_TG_CMIG3 INT_ATU3_TG_CMIG3, //;H'C80 ATU3_TG_CMIG4 INT_ATU3_TG_CMIG4, //;H'CA0 ATU3_TG_CMIG5 INT_ATU3_TG_CMIG5, //;H'CC0 Reserved INT_ReservedCC0, //;H'CE0 Reserved INT_ReservedCE0, //;H'D00 ATU3_TOU_TOU00UDF INT_ATU3_TOU_TOU00UDF, //;H'D20 ATU3_TOU_TOU01UDF INT_ATU3_TOU_TOU01UDF, //;H'D40 ATU3_TOU_TOU02UDF INT_ATU3_TOU_TOU02UDF, //;H'D60 ATU3_TOU_TOU03UDF INT_ATU3_TOU_TOU03UDF, //;H'D80 ATU3_TOU_TOU04UDF INT_ATU3_TOU_TOU04UDF, //;H'DA0 ATU3_TOU_TOU05UDF INT_ATU3_TOU_TOU05UDF, //;H'DC0 ATU3_TOU_TOU06UDF INT_ATU3_TOU_TOU06UDF, //;H'DE0 ATU3_TOU_TOU07UDF INT_ATU3_TOU_TOU07UDF, //;H'E00 ATU3_TOU_TOU10UDF INT_ATU3_TOU_TOU10UDF, //;H'E20 ATU3_TOU_TOU11UDF INT_ATU3_TOU_TOU11UDF, //;H'E40 ATU3_TOU_TOU12UDF INT_ATU3_TOU_TOU12UDF, //;H'E60 ATU3_TOU_TOU13UDF INT_ATU3_TOU_TOU13UDF, //;H'E80 ATU3_TOU_TOU14UDF INT_ATU3_TOU_TOU14UDF, //;H'EA0 ATU3_TOU_TOU15UDF INT_ATU3_TOU_TOU15UDF, //;H'EC0 ATU3_TOU_TOU16UDF INT_ATU3_TOU_TOU16UDF, //;H'EE0 ATU3_TOU_TOU17UDF INT_ATU3_TOU_TOU17UDF, //;H'F00 ATU3_TOU_TOU20UDF INT_ATU3_TOU_TOU20UDF, //;H'F20 ATU3_TOU_TOU21UDF INT_ATU3_TOU_TOU21UDF, //;H'F40 ATU3_TOU_TOU22UDF INT_ATU3_TOU_TOU22UDF, //;H'F60 ATU3_TOU_TOU23UDF INT_ATU3_TOU_TOU23UDF, //;H'F80 ATU3_TOU_TOU24UDF INT_ATU3_TOU_TOU24UDF, //;H'FA0 ATU3_TOU_TOU25UDF INT_ATU3_TOU_TOU25UDF, //;H'FC0 ATU3_TOU_TOU26UDF INT_ATU3_TOU_TOU26UDF, //;H'FE0 ATU3_TOU_TOU27UDF INT_ATU3_TOU_TOU27UDF, //;H'1000 ATU3_TOU_TOU30UDF INT_ATU3_TOU_TOU30UDF, //;H'1020 ATU3_TOU_TOU31UDF INT_ATU3_TOU_TOU31UDF, //;H'1040 ATU3_TOU_TOU32UDF INT_ATU3_TOU_TOU32UDF, //;H'1060 ATU3_TOU_TOU33UDF INT_ATU3_TOU_TOU33UDF, //;H'1080 ATU3_TOU_TOU34UDF INT_ATU3_TOU_TOU34UDF, //;H'10A0 ATU3_TOU_TOU35UDF INT_ATU3_TOU_TOU35UDF, //;H'10C0 ATU3_TOU_TOU36UDF INT_ATU3_TOU_TOU36UDF, //;H'10E0 ATU3_TOU_TOU37UDF INT_ATU3_TOU_TOU37UDF, //;H'1100 ATU3_TOU_TOU40UDF INT_ATU3_TOU_TOU40UDF, //;H'1120 ATU3_TOU_TOU41UDF INT_ATU3_TOU_TOU41UDF, //;H'1140 ATU3_TOU_TOU42UDF INT_ATU3_TOU_TOU42UDF, //;H'1160 ATU3_TOU_TOU43UDF INT_ATU3_TOU_TOU43UDF, //;H'1180 ATU3_TOU_TOU44UDF INT_ATU3_TOU_TOU44UDF, //;H'11A0 ATU3_TOU_TOU45UDF INT_ATU3_TOU_TOU45UDF, //;H'11C0 ATU3_TOU_TOU46UDF INT_ATU3_TOU_TOU46UDF, //;H'11E0 ATU3_TOU_TOU47UDF INT_ATU3_TOU_TOU47UDF, //;H'1200 SCIF_ERI0 INT_SCIF_ERI0, //;H'1220 SCIF_RXI0 INT_SCIF_RXI0, //;H'1240 SCIF_BRI0 INT_SCIF_BRI0, //;H'1260 SCIF_TXI0 INT_SCIF_TXI0, //;H'1280 SCIF_ERI1 INT_SCIF_ERI1, //;H'12A0 SCIF_RXI1 INT_SCIF_RXI1, //;H'12C0 SCIF_BRI1 INT_SCIF_BRI1, //;H'12E0 SCIF_TXI1 INT_SCIF_TXI1, //;H'1300 SCIF_ERI2 INT_SCIF_ERI2, //;H'1320 SCIF_RXI2 INT_SCIF_RXI2, //;H'1340 SCIF_BRI2 INT_SCIF_BRI2, //;H'1360 SCIF_TXI2 INT_SCIF_TXI2, //;H'1380 SCIF_ERI3 INT_SCIF_ERI3, //;H'13A0 SCIF_RXI3 INT_SCIF_RXI3, //;H'13C0 SCIF_BRI3 INT_SCIF_BRI3, //;H'13E0 SCIF_TXI3 INT_SCIF_TXI3, //;H'1400 RSPI_SPEI0 INT_RSPI_SPEI0, //;H'1420 RSPI_SPRI0 INT_RSPI_SPRI0, //;H'1440 RSPI_SPTI0 INT_RSPI_SPTI0, //;H'1460 RSPI_SPEI1 INT_RSPI_SPEI1, //;H'1480 RSPI_SPRI1 INT_RSPI_SPRI1, //;H'14A0 RSPI_SPTI1 INT_RSPI_SPTI1, //;H'14C0 RSPI_SPEI2 INT_RSPI_SPEI2, //;H'14E0 RSPI_SPRI2 INT_RSPI_SPRI2, //;H'1500 RSPI_SPTI2 INT_RSPI_SPTI2, //;H'1520 Reserved INT_Reserved1520, //;H'1540 Reserved INT_Reserved1540, //;H'1560 Reserved INT_Reserved1560, //;H'1580 Reserved INT_Reserved1580, //;H'15A0 Reserved INT_Reserved15A0, //;H'15C0 Reserved INT_Reserved15C0, //;H'15E0 Reserved INT_Reserved15E0, //;H'1600 IIC3_IICI INT_IIC3_IICI, //;H'1620 Reserved INT_Reserved1620, //;H'1640 Reserved INT_Reserved1640, //;H'1660 Reserved INT_Reserved1660, //;H'1680 Reserved INT_Reserved1680, //;H'16A0 Reserved INT_Reserved16A0, //;H'16C0 Reserved INT_Reserved16C0, //;H'16E0 Reserved INT_Reserved16E0, //;H'1700 DRI_DRI0EVENT INT_DRI_DRI0EVENT, //;H'1720 DRI_DRI0DEC INT_DRI_DRI0DEC, //;H'1740 DRI_DRI0TRM INT_DRI_DRI0TRM, //;H'1760 DRI_DRI1EVENT INT_DRI_DRI1EVENT, //;H'1780 DRI_DRI1DEC INT_DRI_DRI1DEC, //;H'17A0 DRI_DRI1TRM INT_DRI_DRI1TRM, //;H'17C0 DRI_DRI2EVENT INT_DRI_DRI2EVENT, //;H'17E0 DRI_DRI2DEC INT_DRI_DRI2DEC, //;H'1800 DRI_DRI2TRM INT_DRI_DRI2TRM, //;H'1820 DRO_DRO INT_DRO_DRO, //;H'1840 Reserved INT_Reserved1840, //;H'1860 Reserved INT_Reserved1860, //;H'1880 Reserved INT_Reserved1880, //;H'18A0 Reserved INT_Reserved18A0, //;H'18C0 Reserved INT_Reserved18C0, //;H'18E0 Reserved INT_Reserved18E0, //;H'1900 FlexRay_FRINT0 INT_FlexRay_FRINT0, //;H'1920 FlexRay_FRINT1 INT_FlexRay_FRINT1, //;H'1940 FlexRay_FRTINT0 INT_FlexRay_FRTINT0, //;H'1960 FlexRay_FRTINT1 INT_FlexRay_FRTINT1, //;H'1980 Reserved INT_Reserved1980, //;H'19A0 Reserved INT_Reserved19A0, //;H'19C0 Reserved INT_Reserved19C0, //;H'19E0 Reserved INT_Reserved19E0, //;H'1A00 CAN_ERS0 INT_CAN_ERS0, //;H'1A20 CAN_RXF0 INT_CAN_RXF0, //;H'1A40 CAN_TXF0 INT_CAN_TXF0, //;H'1A60 Reserved INT_Reserved1A60, //;H'1A80 CAN_RXM00 INT_CAN_RXM00, //;H'1AA0 CAN_RXM10 INT_CAN_RXM10, //;H'1AC0 CAN_TXM0 INT_CAN_TXM0, //;H'1AE0 Reserved INT_Reserved1AE0, //;H'1B00 CAN_ERS1 INT_CAN_ERS1, //;H'1B20 CAN_RXF1 INT_CAN_RXF1, //;H'1B40 CAN_TXF1 INT_CAN_TXF1, //;H'1B60 Reserved INT_Reserved1B60, //;H'1B80 CAN_RXM01 INT_CAN_RXM01, //;H'1BA0 CAN_RXM11 INT_CAN_RXM11, //;H'1BC0 CAN_TXM1 INT_CAN_TXM1, //;H'1BE0 Reserved INT_Reserved1BE0, //;H'1C00 CAN_ERS2 INT_CAN_ERS2, //;H'1C20 CAN_RXF2 INT_CAN_RXF2, //;H'1C40 CAN_TXF2 INT_CAN_TXF2, //;H'1C60 Reserved INT_Reserved1C60, //;H'1C80 CAN_RXM02 INT_CAN_RXM02, //;H'1CA0 CAN_RXM12 INT_CAN_RXM12, //;H'1CC0 CAN_TXM2 INT_CAN_TXM2, //;H'1CE0 Reserved INT_Reserved1CE0, //;H'1D00 CAN_ERS3 INT_CAN_ERS3, //;H'1D20 CAN_RXF3 INT_CAN_RXF3, //;H'1D40 CAN_TXF3 INT_CAN_TXF3, //;H'1D60 Reserved INT_Reserved1D60, //;H'1D80 CAN_RXM03 INT_CAN_RXM03, //;H'1DA0 CAN_RXM13 INT_CAN_RXM13, //;H'1DC0 CAN_TXM3 INT_CAN_TXM3, //;H'1EE0 Reserved INT_Reserved1EE0, //;H'1E00 ADC_AD0I INT_ADC_AD0I, //;H'1E20 ADC_AD1I INT_ADC_AD1I, //;H'1E40 ADC_AD0ID0 INT_ADC_AD0ID0, //;H'1E60 ADC_AD0ID1 INT_ADC_AD0ID1, //;H'1E80 ADC_AD0ID2 INT_ADC_AD0ID2, //;H'1EA0 ADC_AD0ID3 INT_ADC_AD0ID3, //;H'1EC0 ADC_AD0ID4 INT_ADC_AD0ID4, //;H'1EE0 ADC_AD0ID5 INT_ADC_AD0ID5, //;H'1F00 ADC_AD0ID6 INT_ADC_AD0ID6, //;H'1F20 ADC_AD0ID7 INT_ADC_AD0ID7, //;H'1F40 ADC_AD0ID8 INT_ADC_AD0ID8, //;H'1F60 ADC_AD0ID9 INT_ADC_AD0ID9, //;H'1F80 ADC_AD0ID10 INT_ADC_AD0ID10, //;H'1FA0 ADC_AD0ID11 INT_ADC_AD0ID11, //;H'1FC0 ADC_AD0ID12 INT_ADC_AD0ID12, //;H'1FE0 ADC_AD0ID13 INT_ADC_AD0ID13, //;H'2000 ADC_AD0ID14 INT_ADC_AD0ID14, //;H'2020 ADC_AD0ID15 INT_ADC_AD0ID15, //;H'2040 ADC_AD1ID0 INT_ADC_AD1ID0, //;H'2060 ADC_AD1ID1 INT_ADC_AD1ID1, //;H'2080 ADC_AD1ID2 INT_ADC_AD1ID2, //;H'20A0 ADC_AD1ID3 INT_ADC_AD1ID3, //;H'20C0 ADC_AD1ID4 INT_ADC_AD1ID4, //;H'20E0 ADC_AD1ID5 INT_ADC_AD1ID5, //;H'2100 ADC_AD1ID6 INT_ADC_AD1ID6, //;H'2120 ADC_AD1ID7 INT_ADC_AD1ID7, //;H'2140 Reserved INT_Reserved2140, //;H'2160 Reserved INT_Reserved2160, //;H'2180 Reserved INT_Reserved2180, //;H'21A0 Reserved INT_Reserved21A0, //;H'21C0 Reserved INT_Reserved21C0, //;H'21E0 Reserved INT_Reserved21E0, //;H'2200 PDAC_PDIINT INT_PDAC_PDIINT, //;H'2220 Reserved INT_Reserved2220, //;H'2240 Reserved INT_Reserved2240, //;H'2260 Reserved INT_Reserved2260, //;H'2280 Reserved INT_Reserved2280, //;H'22A0 Reserved INT_Reserved22A0, //;H'22C0 Reserved INT_Reserved22C0, //;H'22E0 Reserved INT_Reserved22E0, //;H'2300 ATU3_TA_ICIA10 INT_ATU3_TA_ICIA10, //;H'2320 ATU3_TA_ICIA11 INT_ATU3_TA_ICIA11, //;H'2340 ATU3_TA_ICIA12 INT_ATU3_TA_ICIA12, //;H'2360 ATU3_TA_ICIA13 INT_ATU3_TA_ICIA13, //;H'2380 ATU3_TA_ICIA14 INT_ATU3_TA_ICIA14, //;H'23A0 ATU3_TA_ICIA15 INT_ATU3_TA_ICIA15, //;H'23C0 ATU3_TA_OVIA1 INT_ATU3_TA_OVIA1, //;H'23E0 Reserved INT_Reserved23E0, //;H'2400 CAN_ERS4 INT_CAN_ERS4, //;H'2420 CAN_RXF4 INT_CAN_RXF4, //;H'2440 CAN_TXF4 INT_CAN_TXF4, //;H'2460 Reserved INT_Reserved2460, //;H'2480 CAN_RXM04 INT_CAN_RXM04, //;H'24A0 CAN_RXM14 INT_CAN_RXM14, //;H'24C0 CAN_TXM4 INT_CAN_TXM4 };

　 /* Exception handling routines */ .include "env.s" .equ IMASKclr_RBBLclr, (0xCFFFFFFF & 0xFFFFFF0F) .equ MDRBBLset, 0x70000000 .equ INTMASK, 0x000000F0 .extern _Exp_Vectors .global _int_term !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! !* macro definition *! !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! .macro PUSH_EXP_BASE_REG stc.l ssr,@-r15 ! save ssr stc.l spc,@-r15 ! save spc sts.l pr,@-r15 ! save context registers sts.l fpscr,@-r15 ! save fpscr registers stc.l r7_bank,@-r15 stc.l r6_bank,@-r15 stc.l r5_bank,@-r15 stc.l r4_bank,@-r15 stc.l r3_bank,@-r15 stc.l r2_bank,@-r15 stc.l r1_bank,@-r15 stc.l r0_bank,@-r15 .endm ! .macro POP_EXP_BASE_REG ldc.l @r15+,r0_bank ! recover registers ldc.l @r15+,r1_bank ldc.l @r15+,r2_bank ldc.l @r15+,r3_bank ldc.l @r15+,r4_bank ldc.l @r15+,r5_bank ldc.l @r15+,r6_bank ldc.l @r15+,r7_bank lds.l @r15+,fpscr lds.l @r15+,pr ldc.l @r15+,spc ldc.l @r15+,ssr .endm !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! ! reset ! !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! .section RSTHandler,"ax" _ResetHandler: mov.l EXPEVT_temp,r0 mov.l @r0,r0 shlr2 r0 shlr r0 mov.l _RESET_Vectors_temp,r1 add r1,r0 mov.l @r0,r0 jmp @r0 nop .align 4 EXPEVT_temp: .long EXPEVT _RESET_Vectors_temp: .long _start !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! ! exceptional interrupt ! !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! .section INTHandler,"ax" _INTHandlerPRG: _ExpHandler: PUSH_EXP_BASE_REG ! mov.l EXPEVT_temp1,r0 ! set event address mov.l @r0,r1 ! set exception code mov.l _INT_Vectors_temp1,r0 ! set vector table address add #0xC0,r1 ! exception code - h'40 shlr2 r1 shlr r1 mov.l @(r0,r1),r3 ! set interrupt function addr ! mov.l _INT_MASK_temp1,r0 ! interrupt mask table addr shlr2 r1 mov.b @(r0,r1),r1 ! interrupt mask extu.b r1,r1 ! stc sr,r0 ! save sr mov.l IMASKclr_RBBLclr_temp1,r2 ! RB,BL,mask clear data and r2,r0 ! clear mask data or r1,r0 ! set interrupt mask ldc r0,ssr ! set current status ! ldc r3,spc mov.l _int_term_temp1,r0 ! set interrupt terminate lds r0,pr ! rte nop ! .align 4 EXPEVT_temp1: .long EXPEVT _INT_Vectors_temp1: .long _Exp_Vectors _INT_MASK_temp1: .long INTMASK IMASKclr_RBBLclr_temp1: .long IMASKclr_RBBLclr _int_term_temp1: .long _int_term !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! ! Interrupt terminate ! !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! .align 4 _int_term: mov.l MDRBBLset_temp,r0 ! set MD,BL,RB ldc r0,sr ! POP_EXP_BASE_REG rte ! return nop ! .align 4 MDRBBLset_temp: .long MDRBBLset !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! ! TLB miss interrupt ! !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! .org 0x300 _TLBmissHandler: PUSH_EXP_BASE_REG ! mov.l EXPEVT_temp2,r0 ! set event address mov.l @r0,r1 ! set exception code mov.l _INT_Vectors_temp2,r0 ! set vector table address add #0xC0,r1 ! exception code - h'40 shlr2 r1 shlr r1 mov.l @(r0,r1),r3 ! set interrupt function addr ! mov.l _INT_MASK_temp2,r0 ! interrupt mask table addr shlr2 r1 mov.b @(r0,r1),r1 ! interrupt mask extu.b r1,r1 ! stc sr,r0 ! save sr mov.l IMASKclr_RBBLclr_temp2,r2 ! RB,BL,mask clear data and r2,r0 ! clear mask data or r1,r0 ! set interrupt mask ldc r0,ssr ! set current status ! ldc r3,spc mov.l _int_term_temp2,r0 ! set interrupt terminate lds r0,pr ! rte nop ! .align 4 EXPEVT_temp2: .long EXPEVT _INT_Vectors_temp2: .long _Exp_Vectors _INT_MASK_temp2: .long INTMASK IMASKclr_RBBLclr_temp2: .long IMASKclr_RBBLclr _int_term_temp2: .long _int_term !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! ! IRQ ! !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! .org 0x500 _IRQHandler: PUSH_EXP_BASE_REG ! mov.l INTEVT_temp,r0 ! set event address mov.l @r0,r1 ! set exception code mov.l _INT_Vectors_temp3,r0 ! set vector table address add #0xC0,r1 ! exception code - h'40 shlr2 r1 shlr r1 mov.l @(r0,r1),r3 ! set interrupt function addr ! mov.l _INT_MASK_temp3,r0 ! interrupt mask table addr shlr2 r1 mov.b @(r0,r1),r1 ! interrupt mask extu.b r1,r1 ! stc sr,r0 ! save sr mov.l IMASKclr_RBBLclr_temp3,r2 ! RB,BL,mask clear data and r2,r0 ! clear mask data or r1,r0 ! set interrupt mask ldc r0,ssr ! set current status ! ldc r3,spc mov.l _int_term_temp3,r0 ! set interrupt terminate lds r0,pr ! rte nop ! .align 4 IMASKclr_RBBLclr_temp3: .long IMASKclr_RBBLclr INTEVT_temp: .long INTEVT _int_term_temp3: .long _int_term _INT_Vectors_temp3: .long _Exp_Vectors _INT_MASK_temp3: .long INTMASK .end

　[Version] Version=1.0 [Mode] DEFAULT_MODE=99 MODE=99_07 [Memory MAP] MAP_99_00=0x00000000,0x001FFFFF,EXT,32,0101 MAP_99_01=0x18000000,0x1807FFFF,EXT,32,0101 MAP_99_02=0xA0000000,0xA01FFFFF,EXT,32,0101 MAP_99_03=0xE0000000,0xE3FFFFFF,I/O,32,0101 MAP_99_04=0xE5000000,0xE501FFFF,LRAM,32,0101 MAP_99_05=0xE5200000,0xE520FFFF,ILRAM,32,0101 MAP_99_06=0xF0000000,0xFFFFFFFF,I/O,32,0101 [Simulator] RESOURCE_99=0x00000000,0x001FFFFF,R/W 0x18000000,0x1807FFFF,R/W 0xE5000000,0xE501FFFF,R/W 0xE5200000,0xE520FFFF,R/W, 0xFC000000,0xFFFFFFFF,R/W SIMIOADR=0x4