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　/***************************************************************************** ; * @file: startup_LPC8xxG++.s ; * @purpose: CMSIS Cortex-M0+ Core Device Startup File ; * for the NXP LPC8xx Device Series ; * @version: V1.0 ; * @date: 16. Aug. 2012 ; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ ; * ; * Copyright (C) 2012 ARM Limited. All rights reserved. ; * ARM Limited (ARM) is supplying this software for use with Cortex-M0+ ; * processor based microcontrollers. This file can be freely distributed ; * within development tools that are supporting such ARM based processors. ; * ; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED ; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF ; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. ; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR ; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. ; * ; *****************************************************************************/ /* ; <h> Stack Configuration ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> */ .equ Stack_Size, 0x00000200 .section ".stack", "w" .align 3 .globl __cs3_stack_mem .globl __cs3_stack_size __cs3_stack_mem: .if Stack_Size .space Stack_Size .endif .size __cs3_stack_mem, . - __cs3_stack_mem .set __cs3_stack_size, . - __cs3_stack_mem /* ; <h> Heap Configuration ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> */ .equ Heap_Size, 0x00000000 .section ".heap", "w" .align 3 .globl __cs3_heap_start .globl __cs3_heap_end __cs3_heap_start: .if Heap_Size .space Heap_Size .endif __cs3_heap_end: /* ; <e> Use Code Read Protection ; <o1> Code Read Protection <0xFFFFFFFF=>CRP Disabled ; <0x12345678=>CRP Level 1 ; <0x87654321=>CRP Level 2 ; <0x43218765=>CRP Level 3 (ARE YOU SURE?) ; <0x4E697370=>NO ISP (ARE YOU SURE?) ; </e> */ .equ CRP_Enable, 1 .if CRP_Enable .section ".CRP._0x02FC","a",%progbits .globl CRP_Key .type CRP_Key, %object CRP_Key: .word 0xFFFFFFFF .size CRP_Key, . - CRP_Key .endif /* ; <h> Reset Handler ; <o> Reset Handler Type <0x1=>RAM MODE ; <0x0=>FlashROM(_start) ; <0x2=>FlashROM(main) ; </h> */ .equ Reset_Handler_Type, 0x2 /* ; Vector Table Mapped to Address 0 at Reset */ .section ".cs3.interrupt_vector" .globl __cs3_interrupt_vector_cortex_m .type __cs3_interrupt_vector_cortex_m, %object __cs3_interrupt_vector_cortex_m: .long __cs3_stack @ 00: Top of Stack .long __cs3_reset @ 01: Reset Handler .long NMI_Handler @ 02: NMI Handler .long HardFault_Handler @ 03: Hard Fault Handler .long 0 @ 04: Reserved .long 0 @ 05: Reserved .long 0 @ 06: Reserved .long 0 @ 07: Vector Checksum Validation .long 0 @ 08: Reserved .long 0 @ 09: Reserved .long 0 @ 10: Reserved .long SVC_Handler @ 11: SVCall Handler .long 0 @ 12: Reserved .long 0 @ 13: Reserved .long PendSV_Handler @ 14: PendSV Handler .long SysTick_Handler @ 15: SysTick Handler @ External Interrupts .long SPI0_IRQHandler @ 16+ 0: SPI0 controller .long SPI1_IRQHandler @ 16+ 1: SPI1 controller .long 0 @ 16+ 2: Reserved .long UART0_IRQHandler @ 16+ 3: UART0 .long UART1_IRQHandler @ 16+ 4: UART1 .long UART2_IRQHandler @ 16+ 5: UART2 .long 0 @ 16+ 6: Reserved .long 0 @ 16+ 7: Reserved .long I2C_IRQHandler @ 16+ 8: I2C controller .long SCT_IRQHandler @ 16+ 9: Smart Counter Timer .long MRT_IRQHandler @ 16+10: Multi-Rate Timer .long CMP_IRQHandler @ 16+11: Comparator .long WDT_IRQHandler @ 16+12: PIO1 (0:11) .long BOD_IRQHandler @ 16+13: Brown Out Detect .long 0 @ 16+14: Reserved .long WKT_IRQHandler @ 16+15: Wakeup timer .long 0 @ 16+16: Reserved .long 0 @ 16+17: Reserved .long 0 @ 16+18: Reserved .long 0 @ 16+19: Reserved .long 0 @ 16+20: Reserved .long 0 @ 16+21: Reserved .long 0 @ 16+22: Reserved .long 0 @ 16+23: Reserved .long PININT0_IRQHandler @ 16+24: PIO INT0 .long PININT1_IRQHandler @ 16+25: PIO INT1 .long PININT2_IRQHandler @ 16+26: PIO INT2 .long PININT3_IRQHandler @ 16+27: PIO INT3 .long PININT4_IRQHandler @ 16+28: PIO INT4 .long PININT5_IRQHandler @ 16+29: PIO INT5 .long PININT6_IRQHandler @ 16+30: PIO INT6 .long PININT7_IRQHandler @ 16+31: PIO INT7 .size __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m .thumb /* ; Reset Handler */ .section .cs3.reset,"x",%progbits .thumb_func .globl __cs3_reset_cortex_m .type __cs3_reset_cortex_m, %function __cs3_reset_cortex_m: .fnstart .if (Reset_Handler_Type == 1) @ RAM_MODE /* Clear .bss section (Zero init) */ MOV R0, #0 LDR R1, =__bss_start__ LDR R2, =__bss_end__ LoopZI: CMP R1, R2 BHS BSSIsEmpty STR R0, [R1] ADD R1, #4 B LoopZI BSSIsEmpty: .ifndef __NO_SYSTEM_INIT LDR R0, =SystemInit BLX R0 .endif LDR R0,=main BX R0 .elseif (Reset_Handler_Type == 2) @ Do not use Standerd System Startup Files /* Relocate .data section (Copy from ROM to RAM) */ LDR R1, =_etext LDR R2, =__cs3_region_start_ram LDR R3, =_edata LoopRel: CMP R2, R3 BHS DataIsEmpty LDR R0, [R1] ADD R1, #4 STR R0, [R2] ADD R2, #4 B LoopRel DataIsEmpty: /* Clear .bss section (Zero init) */ MOV R0, #0 LDR R1, =__bss_start__ LDR R2, =__bss_end__ LoopZI: CMP R1, R2 BHS BSSIsEmpty STR R0, [R1] ADD R1, #4 B LoopZI BSSIsEmpty: .ifndef __NO_SYSTEM_INIT LDR R0, =SystemInit BLX R0 .endif LDR R0,=main BX R0 .else @ Use Standerd System Startup Files .ifndef __NO_SYSTEM_INIT LDR R0, =SystemInit BLX R0 .endif LDR R0,=_start BX R0 .endif .pool .cantunwind .fnend .size __cs3_reset_cortex_m,.-__cs3_reset_cortex_m .section ".text" @; Dummy Exception Handlers (infinite loops which can be modified) @; now, under COMMON lpc8xx_nmi.c and lpc8xx_nmi.h, a real NMI handler is created if NMI is enabled @; for particular peripheral. .weak NMI_Handler .type NMI_Handler, %function NMI_Handler: B . .size NMI_Handler, . - NMI_Handler .weak HardFault_Handler .type HardFault_Handler, %function HardFault_Handler: B . .size HardFault_Handler, . - HardFault_Handler .weak SVC_Handler .type SVC_Handler, %function SVC_Handler: B . .size SVC_Handler, . - SVC_Handler .weak PendSV_Handler .type PendSV_Handler, %function PendSV_Handler: B . .size PendSV_Handler, . - PendSV_Handler .weak SysTick_Handler .type SysTick_Handler, %function SysTick_Handler: B . .size SysTick_Handler, . - SysTick_Handler /* IRQ Handlers */ .globl Default_Handler .type Default_Handler, %function Default_Handler: B . .size Default_Handler, . - Default_Handler .macro def_irq_handler handler .weak \handler .set \handler, Default_Handler .endm @ def_irq_handler NMI_Handler def_irq_handler SPI0_IRQHandler def_irq_handler SPI1_IRQHandler def_irq_handler UART0_IRQHandler def_irq_handler UART1_IRQHandler def_irq_handler UART2_IRQHandler def_irq_handler I2C_IRQHandler def_irq_handler SCT_IRQHandler def_irq_handler MRT_IRQHandler def_irq_handler CMP_IRQHandler def_irq_handler WDT_IRQHandler def_irq_handler BOD_IRQHandler def_irq_handler WKT_IRQHandler def_irq_handler PININT0_IRQHandler def_irq_handler PININT1_IRQHandler def_irq_handler PININT2_IRQHandler def_irq_handler PININT3_IRQHandler def_irq_handler PININT4_IRQHandler def_irq_handler PININT5_IRQHandler def_irq_handler PININT6_IRQHandler def_irq_handler PININT7_IRQHandler .end

　/* Linker script for Cortex-M0+ * * Version:CodeSourcery Sourcery G++ Lite 2007q3-53 * BugURL:https://support.codesourcery.com/GNUToolchain/ * * Copyright 2007 CodeSourcery. * * The authors hereby grant permission to use, copy, modify, distribute, * and license this software and its documentation for any purpose, provided * that existing copyright notices are retained in all copies and that this * notice is included verbatim in any distributions. No written agreement, * license, or royalty fee is required for any of the authorized uses. * Modifications to this software may be copyrighted by their authors * and need not follow the licensing terms described here, provided that * the new terms are clearly indicated on the first page of each file where * they apply. */ OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") /*ENTRY(_start)*/ SEARCH_DIR(.) /*GROUP(-lgcc -lc -lcs3 -lcs3unhosted -lcs3micro)*/ GROUP(-lgcc -lcs3unhosted -lcs3micro) MEMORY { rom (rx) : ORIGIN = 0x00000000, LENGTH = 4K ram (rwx) : ORIGIN = 0x10000000, LENGTH = 1K } /* These force the linker to search for particular symbols from * the start of the link process and thus ensure the user's * overrides are picked up */ EXTERN(__cs3_reset_cortex_m) EXTERN(__cs3_interrupt_vector_cortex_m) EXTERN(__cs3_start_c main __cs3_stack __cs3_stack_size __cs3_heap_end) PROVIDE(__cs3_stack = __cs3_region_start_ram + __cs3_region_size_ram); PROVIDE(__cs3_stack_size = __cs3_region_start_ram + __cs3_region_size_ram - _end); PROVIDE(__cs3_heap_start = _end); PROVIDE(__cs3_heap_end = __cs3_region_start_ram + __cs3_region_size_ram); SECTIONS { .text : { CREATE_OBJECT_SYMBOLS __cs3_region_start_rom = .; *(.cs3.region-head.rom) __cs3_interrupt_vector = __cs3_interrupt_vector_cortex_m; *(.cs3.interrupt_vector) /* Make sure we pulled in an interrupt vector. */ ASSERT (. != __cs3_interrupt_vector_cortex_m, "No interrupt vector"); *(.rom) *(.rom.b) __cs3_reset = __cs3_reset_cortex_m; *(.cs3.reset) /* Make sure we pulled in some reset code. */ ASSERT (. != __cs3_reset, "No reset code"); . = DEFINED(CRP_Key) ? 0x02FC : . ; /* NXP only CRP location */ KEEP (*(.CRP.*)) *(.text .text.* .gnu.linkonce.t.*) *(.plt) *(.gnu.warning) *(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.rodata .rodata.* .gnu.linkonce.r.*) *(.ARM.extab* .gnu.linkonce.armextab.*) *(.gcc_except_table) *(.eh_frame_hdr) *(.eh_frame) . = ALIGN(4); KEEP(*(.init)) . = ALIGN(4); __preinit_array_start = .; KEEP (*(.preinit_array)) __preinit_array_end = .; . = ALIGN(4); __init_array_start = .; KEEP (*(SORT(.init_array.*))) KEEP (*(.init_array)) __init_array_end = .; . = ALIGN(0x4); KEEP (*crtbegin.o(.ctors)) KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) KEEP (*(SORT(.ctors.*))) KEEP (*crtend.o(.ctors)) . = ALIGN(4); KEEP(*(.fini)) . = ALIGN(4); __fini_array_start = .; KEEP (*(.fini_array)) KEEP (*(SORT(.fini_array.*))) __fini_array_end = .; KEEP (*crtbegin.o(.dtors)) KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) KEEP (*(SORT(.dtors.*))) KEEP (*crtend.o(.dtors)) . = ALIGN(4); __cs3_regions = .; LONG (0) LONG (__cs3_region_init_ram) LONG (__cs3_region_start_ram) LONG (__cs3_region_init_size_ram) LONG (__cs3_region_zero_size_ram) } /* .ARM.exidx is sorted, so has to go in its own output section. */ __exidx_start = .; .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } >rom __exidx_end = .; .text.align : { . = ALIGN(8); _etext = .; } >rom __cs3_region_size_rom = LENGTH(rom); __cs3_region_num = 1; .data : { __cs3_region_start_ram = .; *(.cs3.region-head.ram) KEEP(*(.jcr)) *(.got.plt) *(.got) *(.shdata) *(.data .data.* .gnu.linkonce.d.*) *(.ram) . = ALIGN (8); _edata = .; } >ram AT>rom .bss : { . = ALIGN (4); __bss_start__ = .; *(.shbss) *(.bss .bss.* .gnu.linkonce.b.*) *(COMMON) *(.ram.b) . = ALIGN (8); __bss_end__ = .; _end = .; __end = .; } >ram AT>rom .heap (NOLOAD) : { *(.heap) } >ram .stack (__cs3_stack - __cs3_stack_size) (NOLOAD): { *(.stack) _estack = .; PROVIDE(estack = .); } >ram __cs3_region_init_ram = LOADADDR (.data); __cs3_region_init_size_ram = _edata - __cs3_region_start_ram; __cs3_region_zero_size_ram = _end - _edata; __cs3_region_size_ram = LENGTH(ram); __cs3_region_num = 1; .stab 0 (NOLOAD) : { *(.stab) } .stabstr 0 (NOLOAD) : { *(.stabstr) } /* DWARF debug sections. * Symbols in the DWARF debugging sections are relative to the beginning * of the section so we begin them at 0. */ /* DWARF 1 */ .debug 0 : { *(.debug) } .line 0 : { *(.line) } /* GNU DWARF 1 extensions */ .debug_srcinfo 0 : { *(.debug_srcinfo) } .debug_sfnames 0 : { *(.debug_sfnames) } /* DWARF 1.1 and DWARF 2 */ .debug_aranges 0 : { *(.debug_aranges) } .debug_pubnames 0 : { *(.debug_pubnames) } /* DWARF 2 */ .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } .debug_abbrev 0 : { *(.debug_abbrev) } .debug_line 0 : { *(.debug_line) } .debug_frame 0 : { *(.debug_frame) } .debug_str 0 : { *(.debug_str) } .debug_loc 0 : { *(.debug_loc) } .debug_macinfo 0 : { *(.debug_macinfo) } /* SGI/MIPS DWARF 2 extensions */ .debug_weaknames 0 : { *(.debug_weaknames) } .debug_funcnames 0 : { *(.debug_funcnames) } .debug_typenames 0 : { *(.debug_typenames) } .debug_varnames 0 : { *(.debug_varnames) } .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) } .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) } /DISCARD/ : { *(.note.GNU-stack) } }