SYSLAB blog

　 .syntax unified .cpu cortex-m0plus .fpu softvfp .thumb /* imported symbols */ /* start address for the initialization values of the .data section. defined in linker script */ .word _sidata /* start address for the .data section. defined in linker script */ .word _sdata /* end address for the .data section. defined in linker script */ .word _edata /* start address for the .bss section. defined in linker script */ .word _sbss /* end address for the .bss section. defined in linker script */ .word _ebss /* initial value of SP. defined in linker script */ .word _estack /* exported symbols */ .global IRQVectorsTable .global Reset_Handler .global _start .global Default_Handler /****************************************************************************** * * The minimal vector table for a Cortex M0+. Note that the proper constructs * must be placed on this to ensure that it ends up at physical address * 0x0000.0000. * ******************************************************************************/ .section .flash_start,"a",%progbits .type IRQVectorsTable, %object .size IRQVectorsTable, .-IRQVectorsTable IRQVectorsTable: .word _estack @ 00: Top of Stack .word Reset_Handler @ 01: Reset Handler .word NMI_Handler @ 02: NMI Handler .word HardFault_Handler @ 03: Hard Fault Handler .word 0 @ 04: Reserved .word 0 @ 05: Reserved .word 0 @ 06: Reserved .word 0 @ 07: Vector Checksum Validation .word 0 @ 08: Reserved .word 0 @ 09: Reserved .word 0 @ 10: Reserved .word SVC_Handler @ 11: SVCall Handler .word 0 @ 12: Reserved .word 0 @ 13: Reserved .word PendSV_Handler @ 14: PendSV Handler .word SysTick_Handler @ 15: SysTick Handler .word SPI0_IRQHandler @ 16+ 0: SPI0 controller .word SPI1_IRQHandler @ 16+ 1: SPI1 controller .word 0 @ 16+ 2: Reserved .word UART0_IRQHandler @ 16+ 3: UART0 .word UART1_IRQHandler @ 16+ 4: UART1 .word UART2_IRQHandler @ 16+ 5: UART2 .word 0 @ 16+ 6: Reserved .word 0 @ 16+ 7: Reserved .word I2C_IRQHandler @ 16+ 8: I2C controller .word SCT_IRQHandler @ 16+ 9: Smart Counter Timer .word MRT_IRQHandler @ 16+10: Multi-Rate Timer .word CMP_IRQHandler @ 16+11: Comparator .word WDT_IRQHandler @ 16+12: PIO1 (0:11) .word BOD_IRQHandler @ 16+13: Brown Out Detect .word 0 @ 16+14: Reserved .word WKT_IRQHandler @ 16+15: Wakeup timer .word 0 @ 16+16: Reserved .word 0 @ 16+17: Reserved .word 0 @ 16+18: Reserved .word 0 @ 16+19: Reserved .word 0 @ 16+20: Reserved .word 0 @ 16+21: Reserved .word 0 @ 16+22: Reserved .word 0 @ 16+23: Reserved .word PININT0_IRQHandler @ 16+24: PIO INT0 .word PININT1_IRQHandler @ 16+25: PIO INT1 .word PININT2_IRQHandler @ 16+26: PIO INT2 .word PININT3_IRQHandler @ 16+27: PIO INT3 .word PININT4_IRQHandler @ 16+28: PIO INT4 .word PININT5_IRQHandler @ 16+29: PIO INT5 .word PININT6_IRQHandler @ 16+30: PIO INT6 .word PININT7_IRQHandler @ 16+31: PIO INT7 /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. * As they are weak aliases, any function with the same name will override * this definition. * *******************************************************************************/ .weak NMI_Handler .thumb_set NMI_Handler, Default_Handler .weak HardFault_Handler .thumb_set HardFault_Handler, Default_Handler .weak SVC_Handler .thumb_set SVC_Handler, Default_Handler .weak PendSV_Handler .thumb_set PendSV_Handler, Default_Handler .weak SysTick_Handler .thumb_set SysTick_Handler, Default_Handler .weak SPI0_IRQHandler .thumb_set SPI0_IRQHandler, Default_Handler .weak SPI1_IRQHandler .thumb_set SPI1_IRQHandler, Default_Handler .weak UART0_IRQHandler .thumb_set UART0_IRQHandler, Default_Handler .weak UART1_IRQHandler .thumb_set UART1_IRQHandler, Default_Handler .weak UART2_IRQHandler .thumb_set UART2_IRQHandler, Default_Handler .weak I2C_IRQHandler .thumb_set I2C_IRQHandler, Default_Handler .weak SCT_IRQHandler .thumb_set SCT_IRQHandler, Default_Handler .weak MRT_IRQHandler .thumb_set MRT_IRQHandler, Default_Handler .weak CMP_IRQHandler .thumb_set CMP_IRQHandler, Default_Handler .weak WDT_IRQHandler .thumb_set WDT_IRQHandler, Default_Handler .weak BOD_IRQHandler .thumb_set BOD_IRQHandler, Default_Handler .weak WKT_IRQHandler .thumb_set WKT_IRQHandler, Default_Handler .weak PININT0_IRQHandler .thumb_set PININT0_IRQHandler, Default_Handler .weak PININT1_IRQHandler .thumb_set PININT1_IRQHandler, Default_Handler .weak PININT2_IRQHandler .thumb_set PININT2_IRQHandler, Default_Handler .weak PININT3_IRQHandler .thumb_set PININT3_IRQHandler, Default_Handler .weak PININT4_IRQHandler .thumb_set PININT4_IRQHandler, Default_Handler .weak PININT5_IRQHandler .thumb_set PININT5_IRQHandler, Default_Handler .weak PININT6_IRQHandler .thumb_set PININT6_IRQHandler, Default_Handler .weak PININT7_IRQHandler .thumb_set PININT7_IRQHandler, Default_Handler .ifdef CRP_Enable /* Code Read Protection */ .equ NOCRP, 0xFFFFFFFF .equ CRP1, 0x12345678 .equ CRP2, 0x87654321 .equ CRP3, 0x43218765 .equ NOISP, 0x4E697370 .section ".crp_patch","a",%progbits .type CRP_Code, %object .globl CRP_Code CRP_Code: .word NOCRP /* NO CRP Protection*/ .size CRP_Code, .-CRP_Code .endif .section .flash_start.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: _start: /* Copy the data segment initializers from flash to SRAM */ ldr r1, =_sidata ldr r2, =_sdata ldr r3, =_edata b LoopCopyDataInit CopyDataInit: ldr r0, [r1] str r0, [r2] adds r1, r1, #4 adds r2, r2, #4 LoopCopyDataInit: cmp r2, r3 bcc CopyDataInit /* Zero fill the bss segment. */ movs r0, #0 ldr r1, =_sbss ldr r2, =_ebss b LoopFillZerobss FillZerobss: str r0, [r1] adds r1, r1, #4 LoopFillZerobss: cmp r1, r2 bcc FillZerobss /* Call the application's entry point.*/ .ifndef __NO_SYSTEM_INIT ldr r0, =SystemInit blx r0 .endif bl main bx lr /* ldr r0, =main bx r0 */ .size Reset_Handler, .-Reset_Handler .section .flash_start.Default_Handler,"ax",%progbits .weak Default_Handler .type Default_Handler, %function Default_Handler: Infinite_Loop: b Infinite_Loop .size Default_Handler, .-Default_Handler

　/* Default secondary/main linker script for Copyright RAISONANCE S.A.S. 2007-2010 !!! This file is automatically generated by Ride if the default linker script option is active !!! Do not modify it if the option is set, as it will be erased at every link. If you need to use your own script please configure your Ride7 project linker options to use your custom linker script You can take this one as example for wrting your custom linker script You can use, copy and distribute this file freely, but without any waranty.*/ INCLUDE "LPC81x_4K_1K_DEF.ld" /* include the common LPCxxx sub-script */ INCLUDE "LPC81x_COMMON.ld" /* include the sections management sub-script for FLASH mode */ INCLUDE "sections_FLASH.ld"

　/*LPCSubFamilyShort Linker subscript for LPC definitions with 4K Flash and 1K RAM Copyright RAISONANCE 2007-2010 !!! This file is automatically generated by Ride !!! Do not modify it, as it will be erased at every link. You can use, copy and distribute this file freely, but without any waranty. */ /* Memory Spaces Definitions */ MEMORY { RAM (xrw) : ORIGIN = 0x10000000, LENGTH = 0x400 STARTFLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x2FC CRPPATCH (r) : ORIGIN = 0x2FC, LENGTH = 4 FLASH (rx) : ORIGIN = 0x00000300, LENGTH = 0xD00 FLASHPATCH (r) : ORIGIN = 0x0, LENGTH = 0 ENDFLASH (rx) : ORIGIN = 0x0, LENGTH = 0x0 FLASHB1 (rx) : ORIGIN = 0x00000000, LENGTH = 0 EXTMEMB0 (rx) : ORIGIN = 0x00000000, LENGTH = 0 EXTMEMB1 (rx) : ORIGIN = 0x00000000, LENGTH = 0 EXTMEMB2 (rx) : ORIGIN = 0x00000000, LENGTH = 0 EXTMEMB3 (rx) : ORIGIN = 0x00000000, LENGTH = 0 } /* higher address of the user mode stack */ _estack = 0x10000400;

　/* Common part of the linker scripts for Cortex LPC devices Copyright RAISONANCE 2011 You can use, modify and distribute thisfile freely, but without any waranty. */ PROVIDE ( _vStackTop = _estack ) ; /* the user mode stack is an exception because we want it at the end of the RAM. therefore, we just check against a minimum. The value below is the minimum memory required for ALL THE STACKS. There will be a link error if there is not this amount of RAM free at the end. */ _Minimum_Stack_Size = 0x80 ;

　/* Common part of the linker scripts for STR71x devices in FLASH mode (that is, the FLASH is seen at 0) Copyright RAISONANCE 2005 You can use, modify and distribute thisfile freely, but without any waranty. */ /* Sections Definitions */ SECTIONS { /* for Cortex devices, the beginning of the startup code is stored in the .isr_vector section, which goes to FLASH */ .isr_vector : { . = ALIGN(4); KEEP(*(.isr_vector)) /* Startup code */ . = ALIGN(4); } >FLASH /* for Cortex LPC devices, the CRP forces to have a separate region for the vectors at the beginning of the falsh */ .flash_start : { . = ALIGN(4); KEEP(*(.flash_start)) /* vectors */ KEEP(*(.flash_start.*)) /* rest of startup */ . = ALIGN(4); } >STARTFLASH /* for Cortex LPC devices, the CRP contains a code to protect the flash */ .crp_patch : { . = ALIGN(4); KEEP(*(.crp_patch)) /* CRP word */ . = ALIGN(4); } >CRPPATCH /* for some STRx devices, the beginning of the startup code is stored in the .flashtext section, which goes to FLASH */ .flashtext : { . = ALIGN(4); *(.flashtext) /* Startup code */ . = ALIGN(4); } >FLASH /* the program code is stored in the .text section, which goes to Flash */ .text : { . = ALIGN(4); *(.text) /* remaining code */ *(.text.*) /* remaining code */ *(.rodata) /* read-only data (constants) */ *(.rodata*) *(.glue_7) *(.glue_7t) . = ALIGN(4); _etext = .; /* This is used by the startup in order to initialize the .data secion */ _sidata = _etext; } >FLASH /* for some LPC devices, there is a FLASH patch to place at a specified address */ .flashpatch : { . = ALIGN(4); KEEP(*(.flashpatch)) /* flashpatch data */ . = ALIGN(4); } >FLASHPATCH /* for some LPC devices, there is a FLASH patch to place at a specified address and then there is the rest of the flash */ .endflash : { . = ALIGN(4); *(.endflash) /* endflash code */ . = ALIGN(4); _e_endflash = . ; } >ENDFLASH /* This is the initialized data section The program executes knowing that the data is in the RAM but the loader puts the initial values in the FLASH (inidata). It is one task of the startup to copy the initial values from FLASH to RAM. */ .data : AT ( _sidata ) { . = ALIGN(4); /* This is used by the startup in order to initialize the .data secion */ _sdata = . ; _data = . ; *(.data) *(.data.*) *(.RAMtext) . = ALIGN(4); /* This is used by the startup in order to initialize the .data secion */ _edata = . ; } >RAM /*calculate end address of idata*/ _eidata = _sidata + (_edata - _sdata); /*check that idata remains in FLASH region*/ _lastdataromaddress = ORIGIN(FLASH) + LENGTH(FLASH); toobig = ( _eidata > _lastdataromaddress) ? "!!!!!!!!! FLASH IS FULL !!!!!!!!!" : 0 ; /* This is the uninitialized data section */ .bss : { . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _sbss = .; _bss = .; *(.bss) *(COMMON) . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; } >RAM PROVIDE ( end = _ebss ); PROVIDE ( _end = _ebss ); /* This is the user stack section This is just to check that there is enough RAM left for the User mode stack It should generate an error if it's full. */ ._usrstack : { . = ALIGN(4); _susrstack = . ; . = . + _Minimum_Stack_Size ; . = ALIGN(4); _eusrstack = . ; } >RAM /* this is the FLASH Bank1 */ /* the C or assembly source must explicitly place the code or data there using the "section" attribute */ .b1text : { *(.b1text) /* remaining code */ *(.b1rodata) /* read-only data (constants) */ *(.b1rodata*) } >FLASHB1 /* this is the EXTMEM */ /* the C or assembly source must explicitly place the code or data there using the "section" attribute */ /* EXTMEM Bank0 */ .eb0text : { *(.eb0text) /* remaining code */ *(.eb0rodata) /* read-only data (constants) */ *(.eb0rodata*) } >EXTMEMB0 /* EXTMEM Bank1 */ .eb1text : { *(.eb1text) /* remaining code */ *(.eb1rodata) /* read-only data (constants) */ *(.eb1rodata*) } >EXTMEMB1 /* EXTMEM Bank2 */ .eb2text : { *(.eb2text) /* remaining code */ *(.eb2rodata) /* read-only data (constants) */ *(.eb2rodata*) } >EXTMEMB2 /* EXTMEM Bank0 */ .eb3text : { *(.eb3text) /* remaining code */ *(.eb3rodata) /* read-only data (constants) */ *(.eb3rodata*) } >EXTMEMB3 __exidx_start = .; __exidx_end = .; /* after that it's only debugging information. */ /* remove the debugging information from the standard libraries */ /DISCARD/ : { libc.a ( * ) libm.a ( * ) libgcc.a ( * ) } /* Stabs debugging sections. */ .stab 0 : { *(.stab) } .stabstr 0 : { *(.stabstr) } .stab.excl 0 : { *(.stab.excl) } .stab.exclstr 0 : { *(.stab.exclstr) } .stab.index 0 : { *(.stab.index) } .stab.indexstr 0 : { *(.stab.indexstr) } .comment 0 : { *(.comment) } /* DWARF debug sections. Symbols in the DWARF debugging sections are relative to the beginning of the section so we begin them at 0. */ /* DWARF 1 */ .debug 0 : { *(.debug) } .line 0 : { *(.line) } /* GNU DWARF 1 extensions */ .debug_srcinfo 0 : { *(.debug_srcinfo) } .debug_sfnames 0 : { *(.debug_sfnames) } /* DWARF 1.1 and DWARF 2 */ .debug_aranges 0 : { *(.debug_aranges) } .debug_pubnames 0 : { *(.debug_pubnames) } /* DWARF 2 */ .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } .debug_abbrev 0 : { *(.debug_abbrev) } .debug_line 0 : { *(.debug_line) } .debug_frame 0 : { *(.debug_frame) } .debug_str 0 : { *(.debug_str) } .debug_loc 0 : { *(.debug_loc) } .debug_macinfo 0 : { *(.debug_macinfo) } /* SGI/MIPS DWARF 2 extensions */ .debug_weaknames 0 : { *(.debug_weaknames) } .debug_funcnames 0 : { *(.debug_funcnames) } .debug_typenames 0 : { *(.debug_typenames) } .debug_varnames 0 : { *(.debug_varnames) } }

　/* * datasheet: http://www.nxp.com/documents/data_sheet/LPC81XM.pdf * user manual: http://www.nxp.com/documents/user_manual/UM10601.pdf * swtich matrix tool: http://www.lpcware.com/content/nxpfile/nxp-switch-matrix-tool-lpc800 (for pin configuration) * * * ISP: When pin PIO0_1 is pulled LOW on reset, the part enters ISP mode and the ISP command handler starts up. * In ISP mode, pin PIO0_0 is connected to function U0_RXD and pin PIO0_4 is connected to function U0_TXD on the USART0 block. */ #include "LPC8xx.h" volatile uint32_t msTicks = 0; void SysTick_Handler(void) { msTicks++; } void delay_ms(uint32_t ms) { uint32_t now = msTicks; while ((msTicks-now) < ms); } #define LED 2 int main(void) { LPC_SWM->PINENABLE0 = 0xffffffbfUL; SysTick_Config(24000);// 24Mhz / 1000 LPC_GPIO_PORT->DIR0 |= 1<<LED; // set pin as output while (1) { LPC_GPIO_PORT->SET0 = 1<<LED; // LED output high delay_ms(50); LPC_GPIO_PORT->CLR0 = 1<<LED; // LED output low delay_ms(200); } }