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　 /***************************************************************************** ; * LPC2300.S: Startup file for Philips LPC2300 device series * ; ***************************************************************************** ; * <<< Use Configuration Wizard in Context Menu >>> * ; ***************************************************************************** ; * This file is part of the uVision/ARM development tools. * ; * Copyright (c) 2007 Keil - An ARM Company. All rights reserved. * ; * This software may only be used under the terms of a valid, current, * ; * end user licence from KEIL for a compatible version of KEIL software * ; * development tools. Nothing else gives you the right to use this software. * *****************************************************************************/ /* * The LPC2300.S code is executed after CPU Reset. This file may be * translated with the following SET symbols. In uVision these SET * symbols are entered under Options - ASM - Define. * * NO_CLOCK_SETUP: when set the startup code will not initialize Clock * (used mostly when clock is already initialized from script .ini * file). * * NO_EMC_SETUP: when set the startup code will not initializes External * Memory Controller (used mostly when external memory is already initialized * and loaded from script .ini file). * * RAM_INTVEC: when set the startup code copies exception vectors * from on-chip Flash to on-chip RAM. * * REMAP: when set the startup code initializes the register MEMMAP * which overwrites the settings of the CPU configuration pins. The * startup and interrupt vectors are remapped from: * 0x00000000 default setting (not remapped) * 0x40000000 when RAM_MODE is used * 0x80000000 when EXTMEM_MODE is used * * EXTMEM_MODE: when set the device is configured for code execution * from external memory starting at address 0x80000000. * * RAM_MODE: when set the device is configured for code execution * from on-chip RAM starting at address 0x40000000. */ @ Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs .equ Mode_USR, 0x10 .equ Mode_FIQ, 0x11 .equ Mode_IRQ, 0x12 .equ Mode_SVC, 0x13 .equ Mode_ABT, 0x17 .equ Mode_UND, 0x1B .equ Mode_SYS, 0x1F .equ I_Bit, 0x80 @ when I bit is set, IRQ is disabled .equ F_Bit, 0x40 @ when F bit is set, FIQ is disabled @----------------------- Memory Definitions ------------------------------------ @ Internal Memory Base Addresses .equ FLASH_BASE, 0x00000000 .equ RAM_BASE, 0x40000000 .equ EXTMEM_BASE, 0x80000000 @ External Memory Base Addresses .equ STA_MEM0_BASE, 0x80000000 .equ STA_MEM1_BASE, 0x81000000 @----------------------- Stack and Heap Definitions ---------------------------- /* ;// <h> Stack Configuration (Stack Sizes in Bytes) ;// <o0> Undefined Mode <0x0-0xFFFFFFFF:8> ;// <o1> Supervisor Mode <0x0-0xFFFFFFFF:8> ;// <o2> Abort Mode <0x0-0xFFFFFFFF:8> ;// <o3> Fast Interrupt Mode <0x0-0xFFFFFFFF:8> ;// <o4> Interrupt Mode <0x0-0xFFFFFFFF:8> ;// <o5> User/System Mode <0x0-0xFFFFFFFF:8> ;// </h> */ .equ UND_Stack_Size, 0x00000000 .equ SVC_Stack_Size, 0x00000080 .equ ABT_Stack_Size, 0x00000000 .equ FIQ_Stack_Size, 0x00000000 .equ IRQ_Stack_Size, 0x00000080 .equ USR_Stack_Size, 0x00000400 .equ ISR_Stack_Size, (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + FIQ_Stack_Size + IRQ_Stack_Size) .section .stack, "w" .align 3 .globl __cs3_stack_mem .globl __cs3_stack_size __cs3_stack_mem: .if USR_Stack_Size .space USR_Stack_Size .endif __initial_sp: .if ISR_Stack_Size .space ISR_Stack_Size .endif .size __cs3_stack_mem, . - __cs3_stack_mem .set __cs3_stack_size, . - __cs3_stack_mem /* ;// <h> Heap Configuration ;// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF> ;// </h> */ .equ Heap_Size, 0x00000400 .section ".heap", "w" .align 3 .globl __cs3_heap_start .globl __cs3_heap_end __cs3_heap_start: .if Heap_Size .space Heap_Size .endif __cs3_heap_end: @----------------------- System Control Block (SCB) Module Definitions --------- .equ SCB_BASE, 0xE01FC000 @ SCB Base Address .equ PLLCON_OFS, 0x80 @ PLL Control Offset .equ PLLCFG_OFS, 0x84 @ PLL Configuration Offset .equ PLLSTAT_OFS, 0x88 @ PLL Status Offset .equ PLLFEED_OFS, 0x8C @ PLL Feed Offset .equ CCLKCFG_OFS, 0x104 @ CPU Clock Divider Reg Offset .equ USBCLKCFG_OFS, 0x108 @ USB Clock Divider Reg Offset .equ CLKSRCSEL_OFS, 0x10C @ Clock Source Select Reg Offset .equ SCS_OFS, 0x1A0 @ System Control and Status Reg Offset .equ PCLKSEL0_OFS, 0x1A8 @ Peripheral Clock Select Reg 0 Offset .equ PCLKSEL1_OFS, 0x1AC @ Peripheral Clock Select Reg 1 Offset .equ PCON_OFS, 0x0C0 @ Power Mode Control Reg Offset .equ PCONP_OFS, 0x0C4 @ Power Control for Periphs Reg Offset @ Constants .equ OSCRANGE, (1<<4) @ Oscillator Range Select .equ OSCEN, (1<<5) @ Main oscillator Enable .equ OSCSTAT, (1<<6) @ Main Oscillator Status .equ PLLCON_PLLE, (1<<0) @ PLL Enable .equ PLLCON_PLLC, (1<<1) @ PLL Connect .equ PLLSTAT_M, (0x7FFF<<0) @ PLL M Value .equ PLLSTAT_N, (0xFF<<16) @ PLL N Value .equ PLLSTAT_PLOCK, (1<<26) @ PLL Lock Status /* ;// <e> Clock Setup ;// <h> System Controls and Status Register (SCS) ;// <o1.4> OSCRANGE: Main Oscillator Range Select ;// <0=> 1 MHz to 20 MHz ;// <1=> 15 MHz to 24 MHz ;// <o1.5> OSCEN: Main Oscillator Enable ;// ;// </h> ;// ;// <h> Clock Source Select Register (CLKSRCSEL) ;// <o2.0..1> CLKSRC: PLL Clock Source Selection ;// <0=> Internal RC oscillator ;// <1=> Main oscillator ;// <2=> RTC oscillator ;// </h> ;// ;// <h> PLL Configuration Register (PLLCFG) ;// <i> PLL_clk = (2* M * PLL_clk_src) / N ;// <o3.0..14> MSEL: PLL Multiplier Selection ;// <1-32768><#-1> ;// <i> M Value ;// <o3.16..23> NSEL: PLL Divider Selection ;// <1-256><#-1> ;// <i> N Value ;// </h> ;// ;// <h> CPU Clock Configuration Register (CCLKCFG) ;// <o4.0..7> CCLKSEL: Divide Value for CPU Clock from PLL ;// <2-256:2><#-1> ;// </h> ;// ;// <h> USB Clock Configuration Register (USBCLKCFG) ;// <o5.0..3> USBSEL: Divide Value for USB Clock from PLL ;// <1-16><#-1> ;// </h> ;// ;// <h> Peripheral Clock Selection Register 0 (PCLKSEL0) ;// <o6.0..1> PCLK_WDT: Peripheral Clock Selection for WDT ;// <0=> Pclk = Cclk / 4 ;// <1=> Pclk = Cclk ;// <2=> Pclk = Cclk / 2 ;// <3=> Pclk = Hclk / 8 ;// <o6.2..3> PCLK_TIMER0: Peripheral Clock Selection for TIMER0 ;// <0=> Pclk = Cclk / 4 ;// <1=> Pclk = Cclk ;// <2=> Pclk = Cclk / 2 ;// <3=> Pclk = Hclk / 8 ;// <o6.4..5> PCLK_TIMER1: Peripheral Clock Selection for TIMER1 ;// <0=> Pclk = Cclk / 4 ;// <1=> Pclk = Cclk ;// <2=> Pclk = Cclk / 2 ;// <3=> Pclk = Hclk / 8 ;// <o6.6..7> PCLK_UART0: Peripheral Clock Selection for UART0 ;// <0=> Pclk = Cclk / 4 ;// <1=> Pclk = Cclk ;// <2=> Pclk = Cclk / 2 ;// <3=> Pclk = Hclk / 8 ;// <o6.8..9> PCLK_UART1: Peripheral Clock Selection for UART1 ;// <0=> Pclk = Cclk / 4 ;// <1=> Pclk = Cclk ;// <2=> Pclk = Cclk / 2 ;// <3=> Pclk = Hclk / 8 ;// <o6.10..11> PCLK_PWM0: Peripheral Clock Selection for PWM0 ;// <0=> Pclk = Cclk / 4 ;// <1=> Pclk = Cclk ;// <2=> Pclk = Cclk / 2 ;// <3=> Pclk = Hclk / 8 ;// <o6.12..13> PCLK_PWM1: Peripheral Clock Selection for PWM1 ;// <0=> Pclk = Cclk / 4 ;// <1=> Pclk = Cclk ;// <2=> Pclk = Cclk / 2 ;// <3=> Pclk = Hclk / 8 ;// <o6.14..15> PCLK_I2C0: Peripheral Clock Selection for I2C0 ;// <0=> Pclk = Cclk / 4 ;// <1=> Pclk = Cclk ;// <2=> Pclk = Cclk / 2 ;// <3=> Pclk = Hclk / 8 ;// <o6.16..17> PCLK_SPI: Peripheral Clock Selection for SPI ;// <0=> Pclk = Cclk / 4 ;// <1=> Pclk = Cclk ;// <2=> Pclk = Cclk / 2 ;// <3=> Pclk = Hclk / 8 ;// <o6.18..19> PCLK_RTC: Peripheral Clock Selection for RTC ;// <0=> Pclk = Cclk / 4 ;// <1=> Pclk = Cclk ;// <2=> Pclk = Cclk / 2 ;// <3=> Pclk = Hclk / 8 ;// <o6.20..21> PCLK_SSP1: Peripheral Clock Selection for SSP1 ;// <0=> Pclk = Cclk / 4 ;// <1=> Pclk = Cclk ;// <2=> Pclk = Cclk / 2 ;// <3=> Pclk = Hclk / 8 ;// <o6.22..23> PCLK_DAC: Peripheral Clock Selection for DAC ;// <0=> Pclk = Cclk / 4 ;// <1=> Pclk = Cclk ;// <2=> Pclk = Cclk / 2 ;// <3=> Pclk = Hclk / 8 ;// <o6.24..25> PCLK_ADC: Peripheral Clock Selection for ADC ;// <0=> Pclk = Cclk / 4 ;// <1=> Pclk = Cclk ;// <2=> Pclk = Cclk / 2 ;// <3=> Pclk = Hclk / 8 ;// <o6.26..27> PCLK_CAN1: Peripheral Clock Selection for CAN1 ;// <0=> Pclk = Cclk / 4 ;// <1=> Pclk = Cclk ;// <2=> Pclk = Cclk / 2 ;// <3=> Pclk = Hclk / 6 ;// <o6.28..29> PCLK_CAN2: Peripheral Clock Selection for CAN2 ;// <0=> Pclk = Cclk / 4 ;// <1=> Pclk = Cclk ;// <2=> Pclk = Cclk / 2 ;// <3=> Pclk = Hclk / 6 ;// <o6.30..31> PCLK_ACF: Peripheral Clock Selection for ACF ;// <0=> Pclk = Cclk / 4 ;// <1=> Pclk = Cclk ;// <2=> Pclk = Cclk / 2 ;// <3=> Pclk = Hclk / 6 ;// </h> ;// ;// <h> Peripheral Clock Selection Register 1 (PCLKSEL1) ;// <o7.0..1> PCLK_BAT_RAM: Peripheral Clock Selection for the Battery Supported RAM ;// <0=> Pclk = Cclk / 4 ;// <1=> Pclk = Cclk ;// <2=> Pclk = Cclk / 2 ;// <3=> Pclk = Hclk / 8 ;// <o7.2..3> PCLK_GPIO: Peripheral Clock Selection for GPIOs ;// <0=> Pclk = Cclk / 4 ;// <1=> Pclk = Cclk ;// <2=> Pclk = Cclk / 2 ;// <3=> Pclk = Hclk / 8 ;// <o7.4..5> PCLK_PCB: Peripheral Clock Selection for Pin Connect Block ;// <0=> Pclk = Cclk / 4 ;// <1=> Pclk = Cclk ;// <2=> Pclk = Cclk / 2 ;// <3=> Pclk = Hclk / 8 ;// <o7.6..7> PCLK_I2C1: Peripheral Clock Selection for I2C1 ;// <0=> Pclk = Cclk / 4 ;// <1=> Pclk = Cclk ;// <2=> Pclk = Cclk / 2 ;// <3=> Pclk = Hclk / 8 ;// <o7.10..11> PCLK_SSP0: Peripheral Clock Selection for SSP0 ;// <0=> Pclk = Cclk / 4 ;// <1=> Pclk = Cclk ;// <2=> Pclk = Cclk / 2 ;// <3=> Pclk = Hclk / 8 ;// <o7.12..13> PCLK_TIMER2: Peripheral Clock Selection for TIMER2 ;// <0=> Pclk = Cclk / 4 ;// <1=> Pclk = Cclk ;// <2=> Pclk = Cclk / 2 ;// <3=> Pclk = Hclk / 8 ;// <o7.14..15> PCLK_TIMER3: Peripheral Clock Selection for TIMER3 ;// <0=> Pclk = Cclk / 4 ;// <1=> Pclk = Cclk ;// <2=> Pclk = Cclk / 2 ;// <3=> Pclk = Hclk / 8 ;// <o7.16..17> PCLK_UART2: Peripheral Clock Selection for UART2 ;// <0=> Pclk = Cclk / 4 ;// <1=> Pclk = Cclk ;// <2=> Pclk = Cclk / 2 ;// <3=> Pclk = Hclk / 8 ;// <o7.18..19> PCLK_UART3: Peripheral Clock Selection for UART3 ;// <0=> Pclk = Cclk / 4 ;// <1=> Pclk = Cclk ;// <2=> Pclk = Cclk / 2 ;// <3=> Pclk = Hclk / 8 ;// <o7.20..21> PCLK_I2C2: Peripheral Clock Selection for I2C2 ;// <0=> Pclk = Cclk / 4 ;// <1=> Pclk = Cclk ;// <2=> Pclk = Cclk / 2 ;// <3=> Pclk = Hclk / 8 ;// <o7.22..23> PCLK_I2S: Peripheral Clock Selection for I2S ;// <0=> Pclk = Cclk / 4 ;// <1=> Pclk = Cclk ;// <2=> Pclk = Cclk / 2 ;// <3=> Pclk = Hclk / 8 ;// <o7.24..25> PCLK_MCI: Peripheral Clock Selection for MCI ;// <0=> Pclk = Cclk / 4 ;// <1=> Pclk = Cclk ;// <2=> Pclk = Cclk / 2 ;// <3=> Pclk = Hclk / 8 ;// <o7.28..29> PCLK_SYSCON: Peripheral Clock Selection for System Control Block ;// <0=> Pclk = Cclk / 4 ;// <1=> Pclk = Cclk ;// <2=> Pclk = Cclk / 2 ;// <3=> Pclk = Hclk / 8 ;// </h> ;// <h> Power Control for Peripherals Register (PCONP) ;// <o8.31> PCUSB: USB interface power/clock enable ;// <o8.30> PCENET: Ethernet block power/clock enable ;// <o8.29> PCGPDMA: GP DMA function power/clock enable ;// <o8.28> PCSDC: SD card interface power/clock enable ;// <o8.27> PCI2S: I2S interface power/clock enable ;// <o8.26> PCI2C2: I2C interface 2 power/clock enable ;// <o8.25> PCUART3: UART 3 power/clock enable ;// <o8.24> PCUART2: UART 2 power/clock enable ;// <o8.23> PCTIM3: Timer 3 power/clock enable ;// <o8.22> PCTIM2: Timer 2 power/clock enable ;// <o8.21> PCSSP0: SSP interface 0 power/clock enable ;// <o8.19> PCI2C1: I2C interface 1 power/clock enable ;// <o8.14> PCAN2: CAN controller 2 power/clock enable ;// <o8.13> PCAN1: CAN controller 1 power/clock enable ;// <o8.12> PCAD: A/D converter power/clock enable ;// <o8.11> PCEMC: External memory controller power/clock enable ;// <o8.10> PCSSP1: SSP interface 1 power/clock enable ;// <o8.9> PCRTC: RTC power/clock enable ;// <o8.8> PCSPI: SPI interface power/clock enable ;// <o8.7> PCI2C0: I2C interface 0 power/clock enable ;// <o8.6> PCPWM1: PWM 1 power/clock enable ;// <o8.4> PCUART1: UART 1 power/clock enable ;// <o8.3> PCUART0: UART 0 power/clock enable ;// <o8.2> PCTIM1: Timer/Counter 1 power/clock enable ;// <o8.1> PCTIM0: Timer/Counter 0 power/clock enable ;// </h> ;// </e>*/ .equ CLOCK_SETUP, 0 .equ SCS_Val, 0x00000000 .equ CLKSRCSEL_Val, 0x00000000 .equ PLLCFG_Val, 0x00000006 .equ CCLKCFG_Val, 0x00000003 .equ USBCLKCFG_Val, 0x00000003 .equ PCLKSEL0_Val, 0x00000000 .equ PCLKSEL1_Val, 0x00000000 .equ PCONP_Val, 0x0000001E @----------------------- Memory Accelerator Module (MAM) Definitions ----------- .equ MAM_BASE, 0xE01FC000 @ MAM Base Address .equ MAMCR_OFS, 0x00 @ MAM Control Offset .equ MAMTIM_OFS, 0x04 @ MAM Timing Offset /* ;// <e> MAM Setup ;// <o1.0..1> MAM Control ;// <0=> Disabled ;// <1=> Partially Enabled ;// <2=> Fully Enabled ;// <i> Mode ;// <o2.0..2> MAM Timing ;// <0=> Reserved <1=> 1 <2=> 2 <3=> 3 ;// <4=> 4 <5=> 5 <6=> 6 <7=> 7 ;// <i> Fetch Cycles ;// </e>*/ .equ MAM_SETUP, 1 .equ MAMCR_Val, 0x00000000 .equ MAMTIM_Val, 0x00000007 @----------------------- Pin Connect Block Definitions ------------------------- .equ PCB_BASE, 0xE002C000 @ PCB Base Address .equ PINSEL0_OFS, 0x00 @ PINSEL0 Address Offset .equ PINSEL1_OFS, 0x04 @ PINSEL1 Address Offset .equ PINSEL2_OFS, 0x08 @ PINSEL2 Address Offset .equ PINSEL3_OFS, 0x0C @ PINSEL3 Address Offset .equ PINSEL4_OFS, 0x10 @ PINSEL4 Address Offset .equ PINSEL5_OFS, 0x14 @ PINSEL5 Address Offset .equ PINSEL6_OFS, 0x18 @ PINSEL6 Address Offset .equ PINSEL7_OFS, 0x1C @ PINSEL7 Address Offset .equ PINSEL8_OFS, 0x20 @ PINSEL8 Address Offset .equ PINSEL9_OFS, 0x24 @ PINSEL9 Address Offset .equ PINSEL10_OFS, 0x28 @ PINSEL10 Address Offset @----------------------- External Memory Controller (EMC) Definitons ----------- .equ EMC_BASE, 0xFFE08000 @ EMC Base Address .equ EMC_CTRL_OFS, 0x000 @ EMCControl .equ EMC_STAT_OFS, 0x004 @ EMCStatus .equ EMC_CONFIG_OFS, 0x008 @ EMCConfig .equ EMC_STA_CFG0_OFS, 0x200 @ EMCStaticConfig0 .equ EMC_STA_WWEN0_OFS, 0x204 @ EMCStaticWaitWen0 .equ EMC_STA_WOEN0_OFS, 0x208 @ EMCStaticWaitOen0 .equ EMC_STA_WRD0_OFS, 0x20C @ EMCStaticWaitRd0 .equ EMC_STA_WPAGE0_OFS, 0x210 @ EMCStaticWaitPage0 .equ EMC_STA_WWR0_OFS, 0x214 @ EMCStaticWaitWr0 .equ EMC_STA_WTURN0_OFS, 0x218 @ EMCStaticWaitTurn0 .equ EMC_STA_CFG1_OFS, 0x220 @ EMCStaticConfig1 .equ EMC_STA_WWEN1_OFS, 0x224 @ EMCStaticWaitWen1 .equ EMC_STA_WOEN1_OFS, 0x228 @ EMCStaticWaitOen1 .equ EMC_STA_WRD1_OFS, 0x22C @ EMCStaticWaitRd1 .equ EMC_STA_WPAGE1_OFS, 0x230 @ EMCStaticWaitPage1 .equ EMC_STA_WWR1_OFS, 0x234 @ EMCStaticWaitWr1 .equ EMC_STA_WTURN1_OFS, 0x238 @ EMCStaticWaitTurn1 .equ EMC_STA_EXT_W_OFS, 0x080 @ EMCStaticExtendedWait .equ BUFEN_Const, (1 << 19) @ Buffer enable bit .equ EMC_PCONP_Const, (1 << 11) @ PCONP val to enable power for EMC @ External Memory Pins definitions @ pin functions for external memory interfacing .equ EMC_PINSEL6_Val, 0x00005555 @ D0 .. D7 .equ EMC_PINSEL8_Val, 0x55555555 @ A0 .. A15 .equ EMC_PINSEL9_Val, 0x50090000 @ !OE, !WE (BLS0 because of errata), !CS0, !CS1 /* ;// <e> External Memory Controller Setup (EMC) */ .equ EMC_SETUP, 0 /* ;// <h> EMC Control Register (EMCControl) ;// <i> Controls operation of the memory controller ;// <o0.2> L: Low-power mode enable ;// <o0.1> M: Address mirror enable ;// <o0.0> E: EMC enable ;// </h>*/ .equ EMC_CTRL_Val, 0x00000001 /* ;// <h> EMC Configuration Register (EMCConfig) ;// <o0.0> Endian mode ;// <0=> Little-endian ;// <1=> Big-endian ;// </h>*/ .equ EMC_CONFIG_Val, 0x00000000 /* ;// <e> Configure External Bus Behaviour for Static CS0 Area */ .equ EMC_STACS0_SETUP, 1 /* ;// <h> Static Memory Configuration Register (EMCStaticConfig0) ;// <i> Defines the configuration information for the static memory CS0 ;// <o0.20> WP: Write protect ;// <o0.19> B: Write buffer enable ;// <o0.8> EW: Extended wait enable ;// <o0.6> PC: Chip select polarity ;// <0=> Active LOW chip select ;// <1=> Active HIGH chip select ;// <o0.3> PM: Async page mode enable ;// <o0.0..1> MW: Memory width ;// <0=> 8 bit ;// <1=> 16 bit ;// <2=> 32 bit ;// </h>*/ .equ EMC_STA_CFG0_Val, 0x00000000 /* ;// <h> Static Memory Write Enable Delay Register (EMCStaticWaitWen0) ;// <i> Selects the delay from CS0 to write enable ;// <o.0..3> WAITWEN: Wait write enable <1-16> <#-1> ;// <i> The delay is in CCLK cycles ;// </h>*/ .equ EMC_STA_WWEN0_Val, 0x00000002 /* ;// <h> Static Memory Output Enable Delay register (EMCStaticWaitOen0) ;// <i> Selects the delay from CS0 or address change, whichever is later, to output enable ;// <o.0..3> WAITOEN: Wait output enable <0-15> ;// <i> The delay is in CCLK cycles ;// </h>*/ .equ EMC_STA_WOEN0_Val, 0x00000002 /* ;// <h> Static Memory Read Delay Register (EMCStaticWaitRd0) ;// <i> Selects the delay from CS0 to a read access ;// <o.0..4> WAITRD: Non-page mode read wait states or asynchronous page mode read first access wait states <1-32> <#-1> ;// <i> The delay is in CCLK cycles ;// </h>*/ .equ EMC_STA_WRD0_Val, 0x0000001F /* ;// <h> Static Memory Page Mode Read Delay Register (EMCStaticWaitPage0) ;// <i> Selects the delay for asynchronous page mode sequential accesses for CS0 ;// <o.0..4> WAITPAGE: Asynchronous page mode read after the first read wait states <1-32> <#-1> ;// <i> The delay is in CCLK cycles ;// </h>*/ .equ EMC_STA_WPAGE0_Val, 0x0000001F /* ;// <h> Static Memory Write Delay Register (EMCStaticWaitWr0) ;// <i> Selects the delay from CS0 to a write access ;// <o.0..4> WAITWR: Write wait states <2-33> <#-2> ;// <i> The delay is in CCLK cycles ;// </h>*/ .equ EMC_STA_WWR0_Val, 0x0000001F /* ;// <h> Static Memory Turn Round Delay Register (EMCStaticWaitTurn0) ;// <i> Selects the number of bus turnaround cycles for CS0 ;// <o.0..4> WAITTURN: Bus turnaround cycles <1-16> <#-1> ;// <i> The delay is in CCLK cycles ;// </h>*/ .equ EMC_STA_WTURN0_Val, 0x0000000F /* ;// </e> End of Static Setup for Static CS0 Area ;// <e> Configure External Bus Behaviour for Static CS1 Area */ .equ EMC_STACS1_SETUP, 0 /* ;// <h> Static Memory Configuration Register (EMCStaticConfig1) ;// <i> Defines the configuration information for the static memory CS1 ;// <o0.20> WP: Write protect ;// <o0.19> B: Write buffer enable ;// <o0.8> EW: Extended wait enable ;// <o0.6> PC: Chip select polarity ;// <0=> Active LOW chip select ;// <1=> Active HIGH chip select ;// <o0.3> PM: Async page mode enable ;// <o0.0..1> MW: Memory width ;// <0=> 8 bit ;// <1=> 16 bit ;// <2=> 32 bit ;// </h>*/ .equ EMC_STA_CFG1_Val, 0x00000000 /* ;// <h> Static Memory Write Enable Delay Register (EMCStaticWaitWen1) ;// <i> Selects the delay from CS1 to write enable ;// <o.0..3> WAITWEN: Wait write enable <1-16> <#-1> ;// <i> The delay is in CCLK cycles ;// </h>*/ .equ EMC_STA_WWEN1_Val, 0x00000000 /* ;// <h> Static Memory Output Enable Delay register (EMCStaticWaitOen1) ;// <i> Selects the delay from CS1 or address change, whichever is later, to output enable ;// <o.0..3> WAITOEN: Wait output enable <0-15> ;// <i> The delay is in CCLK cycles ;// </h>*/ .equ EMC_STA_WOEN1_Val, 0x00000000 /* ;// <h> Static Memory Read Delay Register (EMCStaticWaitRd1) ;// <i> Selects the delay from CS1 to a read access ;// <o.0..4> WAITRD: Non-page mode read wait states or asynchronous page mode read first access wait states <1-32> <#-1> ;// <i> The delay is in CCLK cycles ;// </h>*/ .equ EMC_STA_WRD1_Val, 0x0000001F /* ;// <h> Static Memory Page Mode Read Delay Register (EMCStaticWaitPage0) ;// <i> Selects the delay for asynchronous page mode sequential accesses for CS1 ;// <o.0..4> WAITPAGE: Asynchronous page mode read after the first read wait states <1-32> <#-1> ;// <i> The delay is in CCLK cycles ;// </h>*/ .equ EMC_STA_WPAGE1_Val, 0x0000001F /* ;// <h> Static Memory Write Delay Register (EMCStaticWaitWr1) ;// <i> Selects the delay from CS1 to a write access ;// <o.0..4> WAITWR: Write wait states <2-33> <#-2> ;// <i> The delay is in CCLK cycles ;// </h>*/ .equ EMC_STA_WWR1_Val, 0x0000001F /* ;// <h> Static Memory Turn Round Delay Register (EMCStaticWaitTurn1) ;// <i> Selects the number of bus turnaround cycles for CS1 ;// <o.0..4> WAITTURN: Bus turnaround cycles <1-16> <#-1> ;// <i> The delay is in CCLK cycles ;// </h>*/ .equ EMC_STA_WTURN1_Val, 0x0000000F /* ;// </e> End of Static Setup for Static CS1 Area ;// <h> Static Memory Extended Wait Register (EMCStaticExtendedWait) ;// <i> Time long static memory read and write transfers ;// <o.0..9> EXTENDEDWAIT: Extended wait time out <1-64><#-1> ;// <i> The delay is in (16 * CCLK) cycles ;// </h>*/ .equ EMC_STA_EXT_W_Val, 0x00000000 /* ;// </e> End of EMC Setup ; <e> Use Code Read Protection ; <o1> Code Read Protection <0x11223344=>CRP Disabled ; <0x12345678=>CRP Level 1 ; <0x87654321=>CRP Level 2 ; <0x43218765=>CRP Level 3 (ARE YOU SURE?) ; </e>*/ .if 0 .section ".CRP._0x01FC","a",%progbits .globl CRP_Code .type CRP_Code, %object CRP_Code: .word 0x11223344 .size CRP_Code, . - CRP_Code .endif /* ; <e> IRQ Vector from VicVectAddr ; </e>*/ .equ USE_VICVECT, 0 /* ; <h> Reset Handler ; <o> Reset Handler Type <0x1=>RAM MODE ; <0x0=>FlashROM(_start) ; <0x2=>FlashROM(main) ; </h>*/ .equ Reset_Handler_Type, 0 @ PRESERVE8 @ Area Definition and Entry Point @ Startup Code must be linked first at Address at which it expects to run. .arm .section ".cs3.interrupt_vector" .globl __cs3_interrupt_vector_arm .type __cs3_interrupt_vector_arm, %object @ Exception Vectors @ Mapped to Address 0. @ Absolute addressing mode must be used. @ Dummy Handlers are implemented as infinite loops which can be modified. __cs3_interrupt_vector_arm: LDR PC, Reset_Addr LDR PC, Undef_Addr LDR PC, SWI_Addr LDR PC, PAbt_Addr LDR PC, DAbt_Addr .if USE_VICVECT .word 0xB9206E50 @ Vector Checksum Validation LDR PC, [PC, #-0x0120] @ Vector from VicVectAddr .else .word 0xB8A06F58 @ Vector Checksum Validation LDR PC, IRQ_Addr .endif LDR PC, FIQ_Addr Reset_Addr: .word __cs3_reset Undef_Addr: .word Undef_Handler SWI_Addr: .word SWI_Handler PAbt_Addr: .word PAbt_Handler DAbt_Addr: .word DAbt_Handler .word 0 @ Reserved Address IRQ_Addr: .word IRQ_Handler FIQ_Addr: .word FIQ_Handler .size __cs3_interrupt_vector_arm, . - __cs3_interrupt_vector_arm .weak Undef_Handler .type Undef_Handler, %function Undef_Handler: B . .size Undef_Handler, . - Undef_Handler .weak SWI_Handler .type SWI_Handler, %function SWI_Handler: B . .size SWI_Handler, . - SWI_Handler .weak PAbt_Handler .type PAbt_Handler, %function PAbt_Handler: B . .size PAbt_Handler, . - PAbt_Handler .weak DAbt_Handler .type DAbt_Handler, %function DAbt_Handler: B . .size DAbt_Handler, . - DAbt_Handler .weak IRQ_Handler .type IRQ_Handler, %function IRQ_Handler: B . .size IRQ_Handler, . - IRQ_Handler .weak FIQ_Handler .type FIQ_Handler, %function FIQ_Handler: B . .size FIQ_Handler, . - FIQ_Handler @ Reset Handler .section .cs3.reset,"x",%progbits .globl __cs3_reset_arm .type __cs3_reset_arm, %function __cs3_reset_arm: .fnstart @ Clock Setup ------------------------------------------------------------------ .if (CLOCK_SETUP != 0) @ IF (:LNOT:(:DEF:NO_CLOCK_SETUP)):LAND:(CLOCK_SETUP != 0) LDR R0, =SCB_BASE MOV R1, #0xAA MOV R2, #0x55 @ Configure and Enable PLL LDR R3, =SCS_Val @ Enable main oscillator STR R3, [R0, #SCS_OFS] .if (SCS_Val & OSCEN) != 0 OSC_Loop: LDR R3, [R0, #SCS_OFS] @ Wait for main osc stabilize ANDS R3, R3, #OSCSTAT BEQ OSC_Loop .endif LDR R3, =CLKSRCSEL_Val @ Select PLL source clock STR R3, [R0, #CLKSRCSEL_OFS] LDR R3, =PLLCFG_Val STR R3, [R0, #PLLCFG_OFS] STR R1, [R0, #PLLFEED_OFS] STR R2, [R0, #PLLFEED_OFS] MOV R3, #PLLCON_PLLE STR R3, [R0, #PLLCON_OFS] STR R1, [R0, #PLLFEED_OFS] STR R2, [R0, #PLLFEED_OFS] .if (CLKSRCSEL_Val & 3) != 2 @ Wait until PLL Locked (if source is not RTC oscillator) PLL_Loop: LDR R3, [R0, #PLLSTAT_OFS] ANDS R3, R3, #PLLSTAT_PLOCK BEQ PLL_Loop .else @ Wait at least 200 cycles (if source is RTC oscillator) MOV R3, #(200/4) PLL_Loop: SUBS R3, R3, #1 BNE PLL_Loop .endif M_N_Lock: LDR R3, [R0, #PLLSTAT_OFS] LDR R4, =(PLLSTAT_M | PLLSTAT_N) AND R3, R3, R4 LDR R4, =PLLCFG_Val EORS R3, R3, R4 BNE M_N_Lock @ Setup CPU clock divider MOV R3, #CCLKCFG_Val STR R3, [R0, #CCLKCFG_OFS] @ Setup USB clock divider LDR R3, =USBCLKCFG_Val STR R3, [R0, #USBCLKCFG_OFS] @ Setup Peripheral Clock LDR R3, =PCLKSEL0_Val STR R3, [R0, #PCLKSEL0_OFS] LDR R3, =PCLKSEL1_Val STR R3, [R0, #PCLKSEL1_OFS] @ Switch to PLL Clock MOV R3, #(PLLCON_PLLE | PLLCON_PLLC) STR R3, [R0, #PLLCON_OFS] STR R1, [R0, #PLLFEED_OFS] STR R2, [R0, #PLLFEED_OFS] LDR R4, =PCONP_Val @ Enable Peripheral Clocks STR R4, [R0, #PCONP_OFS] .endif @ CLOCK_SETUP @ Setup Memory Accelerator Module ---------------------------------------------- .if MAM_SETUP != 0 LDR R0, =MAM_BASE MOV R1, #MAMTIM_Val STR R1, [R0, #MAMTIM_OFS] MOV R1, #MAMCR_Val STR R1, [R0, #MAMCR_OFS] .endif @ MAM_SETUP @ Setup External Memory Controller --------------------------------------------- .if (EMC_SETUP != 0) @ IF (:DEF:NO_EMC_SETUP):LOR:(EMC_SETUP != 0) LDR R0, =EMC_BASE LDR R1, =SCB_BASE LDR R2, =PCB_BASE LDR R4, [R1, #PCONP_OFS] ORR R4, R4, #EMC_PCONP_Const @ Enable EMC clock STR R4, [R1, #PCONP_OFS] LDR R4, =EMC_CTRL_Val STR R4, [R0, #EMC_CTRL_OFS] LDR R4, =EMC_CONFIG_Val STR R4, [R0, #EMC_CONFIG_OFS] @ Setup pin functions for External Bus functionality LDR R4, =EMC_PINSEL6_Val STR R4, [R2, #PINSEL6_OFS] LDR R4, =EMC_PINSEL8_Val STR R4, [R2, #PINSEL8_OFS] LDR R4, =EMC_PINSEL9_Val STR R4, [R2, #PINSEL9_OFS] LDR R6, =1200000 @ Number of cycles to delay Wait_0: SUBS R6, R6, #1 @ Delay ~100 ms @ proc clk 48 MHz BNE Wait_0 .if (EMC_STACS0_SETUP != 0) LDR R4, =EMC_STA_CFG0_Val STR R4, [R0, #EMC_STA_CFG0_OFS] LDR R4, =EMC_STA_WWEN0_Val STR R4, [R0, #EMC_STA_WWEN0_OFS] LDR R4, =EMC_STA_WOEN0_Val STR R4, [R0, #EMC_STA_WOEN0_OFS] LDR R4, =EMC_STA_WRD0_Val STR R4, [R0, #EMC_STA_WRD0_OFS] LDR R4, =EMC_STA_WPAGE0_Val STR R4, [R0, #EMC_STA_WPAGE0_OFS] LDR R4, =EMC_STA_WWR0_Val STR R4, [R0, #EMC_STA_WWR0_OFS] LDR R4, =EMC_STA_WTURN0_Val STR R4, [R0, #EMC_STA_WTURN0_OFS] .endif .if (EMC_STACS1_SETUP != 0) LDR R4, =EMC_STA_CFG1_Val STR R4, [R0, #EMC_STA_CFG1_OFS] LDR R4, =EMC_STA_WWEN1_Val STR R4, [R0, #EMC_STA_WWEN1_OFS] LDR R4, =EMC_STA_WOEN1_Val STR R4, [R0, #EMC_STA_WOEN1_OFS] LDR R4, =EMC_STA_WRD1_Val STR R4, [R0, #EMC_STA_WRD1_OFS] LDR R4, =EMC_STA_WPAGE1_Val STR R4, [R0, #EMC_STA_WPAGE1_OFS] LDR R4, =EMC_STA_WWR1_Val STR R4, [R0, #EMC_STA_WWR1_OFS] LDR R4, =EMC_STA_WTURN1_Val STR R4, [R0, #EMC_STA_WTURN1_OFS] .endif LDR R6, =120000 @ Number of cycles to delay Wait_1: SUBS R6, R6, #1 @ Delay ~10 ms @ proc clk 48 MHz BNE Wait_1 LDR R4, =EMC_STA_EXT_W_Val LDR R5, =EMC_STA_EXT_W_OFS ADD R5, R5, R0 STR R4, [R5, #0] .endif @ EMC_SETUP @ Copy Exception Vectors to Internal RAM --------------------------------------- .ifdef RAM_INTVEC ADR R8, Vectors @ Source LDR R9, =RAM_BASE @ Destination LDMIA R8!, {R0-R7} @ Load Vectors STMIA R9!, {R0-R7} @ Store Vectors LDMIA R8!, {R0-R7} @ Load Handler Addresses STMIA R9!, {R0-R7} @ Store Handler Addresses .endif @ Memory Mapping (when Interrupt Vectors are in RAM) --------------------------- .equ MEMMAP, 0xE01FC040 @ Memory Mapping Control .ifdef REMAP LDR R0, =MEMMAP .ifdef EXTMEM_MODE @IF :DEF:EXTMEM_MODE MOV R1, #3 .else @ELIF :DEF:RAM_MODE .ifdef RAM_MODE MOV R1, #2 .else @ELSE MOV R1, #1 .endif @ENDIF .endif STR R1, [R0] .endif @ Setup Stack for each mode ---------------------------------------------------- LDR R0, =__cs3_stack @ Enter Undefined Instruction Mode and set its Stack Pointer MSR CPSR_c, #Mode_UND | I_Bit | F_Bit MOV SP, R0 SUB R0, R0, #UND_Stack_Size @ Enter Abort Mode and set its Stack Pointer MSR CPSR_c, #Mode_ABT | I_Bit | F_Bit MOV SP, R0 SUB R0, R0, #ABT_Stack_Size @ Enter FIQ Mode and set its Stack Pointer MSR CPSR_c, #Mode_FIQ | I_Bit | F_Bit MOV SP, R0 SUB R0, R0, #FIQ_Stack_Size @ Enter IRQ Mode and set its Stack Pointer MSR CPSR_c, #Mode_IRQ | I_Bit | F_Bit MOV SP, R0 SUB R0, R0, #IRQ_Stack_Size @ Enter Supervisor Mode and set its Stack Pointer MSR CPSR_c, #Mode_SVC | I_Bit | F_Bit MOV SP, R0 SUB R0, R0, #SVC_Stack_Size @ Enter User Mode and set its Stack Pointer MSR CPSR_c, #Mode_USR MOV SP, R0 SUB SL, SP, #USR_Stack_Size .if (Reset_Handler_Type == 0) @ FlashROM(_start) @ Enter the C code ------------------------------------------------------------- .extern __cs3_start_c LDR R0, =__cs3_start_c @ _start BX R0 .else @ RAM_MODE or FlashROM(main) .if (Reset_Handler_Type == 2) @ FlashROM(main) @ Relocate .data section (Copy from ROM to RAM) LDR R1, =_etext LDR R2, =__cs3_region_start_ram LDR R3, =_edata LoopRel: CMP R2, R3 LDRLO R0, [R1], #4 STRLO R0, [R2], #4 BLO LoopRel .endif @ Clear .bss section (Zero init) MOV R0, #0 LDR R1, =__bss_start__ LDR R2, =__bss_end__ LoopZI: CMP R1, R2 STRLO R0, [R1], #4 BLO LoopZI @ Enter the C code ------------------------------------------------------------- .extern main _start: .globl _start MOV LR,PC LDR PC,=main BX LR NOP .endif .pool .cantunwind .fnend .size __cs3_reset_arm, . - __cs3_reset_arm @ User Initial Stack & Heap .section .text, "ax" .extern __use_two_region_memory .global __user_initial_stackheap .type __user_initial_stackheap, %function __user_initial_stackheap: .fnstart LDR R0, = __cs3_heap_start LDR R1, = (__cs3_stack_mem + USR_Stack_Size) LDR R2, = (__cs3_heap_start + Heap_Size) LDR R3, = __cs3_stack_mem BX LR .pool .cantunwind .fnend .size __user_initial_stackheap, . - __user_initial_stackheap .end

　/* Linker script for ARM7 TDMI-S * * Version:CodeSourcery Sourcery G++ Lite 2007q3-53 * BugURL:https://support.codesourcery.com/GNUToolchain/ * * Copyright 2007 CodeSourcery. * * The authors hereby grant permission to use, copy, modify, distribute, * and license this software and its documentation for any purpose, provided * that existing copyright notices are retained in all copies and that this * notice is included verbatim in any distributions. No written agreement, * license, or royalty fee is required for any of the authorized uses. * Modifications to this software may be copyrighted by their authors * and need not follow the licensing terms described here, provided that * the new terms are clearly indicated on the first page of each file where * they apply. */ OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") ENTRY(_start) SEARCH_DIR(.) GROUP(-lgcc -lc -lcs3 -lcs3unhosted -lcs3arm) MEMORY { rom (rx) : ORIGIN = 0x00000000, LENGTH = 512K ram (rwx) : ORIGIN = 0x40000000, LENGTH = 64K ram1(rwx) : ORIGIN = 0x7FD00000, LENGTH = 16k /* USB RAM */ ram2(rwx) : ORIGIN = 0x7FE00000, LENGTH = 16k /* Ethernet RAM */ /* ram3(rwx) : ORIGIN = 0xE0084000, LENGTH = 2k Battery RAM */ } /* These force the linker to search for particular symbols from * the start of the link process and thus ensure the user's * overrides are picked up */ EXTERN(__cs3_reset_arm) EXTERN(__cs3_interrupt_vector_arm) EXTERN(__cs3_start_c main __cs3_stack __cs3_stack_size __cs3_heap_end) PROVIDE(__cs3_stack = __cs3_region_start_ram + __cs3_region_size_ram); PROVIDE(__cs3_stack_size = __cs3_region_start_ram + __cs3_region_size_ram - _end); PROVIDE(__cs3_heap_start = _end); PROVIDE(__cs3_heap_end = __cs3_region_start_ram + __cs3_region_size_ram); SECTIONS { .text : { CREATE_OBJECT_SYMBOLS __cs3_region_start_rom = .; *(.cs3.region-head.rom) __cs3_interrupt_vector = __cs3_interrupt_vector_arm; *(.cs3.interrupt_vector) /* Make sure we pulled in an interrupt vector. */ ASSERT (. != __cs3_interrupt_vector_arm, "No interrupt vector"); *(.rom) *(.rom.b) __cs3_reset = __cs3_reset_arm; *(.cs3.reset) /* Make sure we pulled in some reset code. */ ASSERT (. != __cs3_reset, "No reset code"); . = DEFINED(CRP_Code) ? 0x01FC : . ; /* NXP only CRP location */ KEEP (*(.CRP.*)) *(.text .text.* .gnu.linkonce.t.*) *(.plt) *(.gnu.warning) *(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.rodata .rodata.* .gnu.linkonce.r.*) *(.ARM.extab* .gnu.linkonce.armextab.*) *(.gcc_except_table) *(.eh_frame_hdr) *(.eh_frame) . = ALIGN(4); KEEP(*(.init)) . = ALIGN(4); __preinit_array_start = .; KEEP (*(.preinit_array)) __preinit_array_end = .; . = ALIGN(4); __init_array_start = .; KEEP (*(SORT(.init_array.*))) KEEP (*(.init_array)) __init_array_end = .; . = ALIGN(0x4); KEEP (*crtbegin.o(.ctors)) KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) KEEP (*(SORT(.ctors.*))) KEEP (*crtend.o(.ctors)) . = ALIGN(4); KEEP(*(.fini)) . = ALIGN(4); __fini_array_start = .; KEEP (*(.fini_array)) KEEP (*(SORT(.fini_array.*))) __fini_array_end = .; KEEP (*crtbegin.o(.dtors)) KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) KEEP (*(SORT(.dtors.*))) KEEP (*crtend.o(.dtors)) . = ALIGN(4); __cs3_regions = .; LONG (0) LONG (__cs3_region_init_ram) LONG (__cs3_region_start_ram) LONG (__cs3_region_init_size_ram) LONG (__cs3_region_zero_size_ram) } /* .ARM.exidx is sorted, so has to go in its own output section. */ __exidx_start = .; .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } >rom __exidx_end = .; .text.align : { . = ALIGN(8); _etext = .; } >rom __cs3_region_size_rom = LENGTH(rom); __cs3_region_num = 1; .data : { __cs3_region_start_ram = .; *(.cs3.region-head.ram) KEEP(*(.jcr)) *(.got.plt) *(.got) *(.shdata) *(.data .data.* .gnu.linkonce.d.*) *(.ram) . = ALIGN (8); _edata = .; } >ram AT>rom .bss : { . = ALIGN (4); __bss_start__ = .; *(.shbss) *(.bss .bss.* .gnu.linkonce.b.*) *(COMMON) *(.ram.b) . = ALIGN (8); __bss_end__ = .; _end = .; __end = .; } >ram AT>rom /* This used for USB RAM section */ .usb_ram (NOLOAD): { *.o (USB_RAM) } > ram2 .heap (NOLOAD) : { *(.heap) } >ram .stack (__cs3_stack - __cs3_stack_size) (NOLOAD): { *(.stack) _estack = .; PROVIDE(estack = .); } >ram __cs3_region_init_ram = LOADADDR (.data); __cs3_region_init_size_ram = _edata - __cs3_region_start_ram; __cs3_region_zero_size_ram = _end - _edata; __cs3_region_size_ram = LENGTH(ram); __cs3_region_num = 1; .stab 0 (NOLOAD) : { *(.stab) } .stabstr 0 (NOLOAD) : { *(.stabstr) } /* DWARF debug sections. * Symbols in the DWARF debugging sections are relative to the beginning * of the section so we begin them at 0. */ /* DWARF 1 */ .debug 0 : { *(.debug) } .line 0 : { *(.line) } /* GNU DWARF 1 extensions */ .debug_srcinfo 0 : { *(.debug_srcinfo) } .debug_sfnames 0 : { *(.debug_sfnames) } /* DWARF 1.1 and DWARF 2 */ .debug_aranges 0 : { *(.debug_aranges) } .debug_pubnames 0 : { *(.debug_pubnames) } /* DWARF 2 */ .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } .debug_abbrev 0 : { *(.debug_abbrev) } .debug_line 0 : { *(.debug_line) } .debug_frame 0 : { *(.debug_frame) } .debug_str 0 : { *(.debug_str) } .debug_loc 0 : { *(.debug_loc) } .debug_macinfo 0 : { *(.debug_macinfo) } /* SGI/MIPS DWARF 2 extensions */ .debug_weaknames 0 : { *(.debug_weaknames) } .debug_funcnames 0 : { *(.debug_funcnames) } .debug_typenames 0 : { *(.debug_typenames) } .debug_varnames 0 : { *(.debug_varnames) } .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) } .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) } /DISCARD/ : { *(.note.GNU-stack) } }

　#include <lpc23xx.h> #define TIMER0_INT 4 #define LED1_MASK (1UL<<18) void __attribute__ ((interrupt ("IRQ"))) IRQ_Handler( void ) { if ( VICIRQStatus & (0x1 << TIMER0_INT) && VICIntEnable & (0x1 << TIMER0_INT) ) { T0IR = 1; /* clear interrupt flag */ FIO1PIN ^= LED1_MASK; } } int main(void) { SCS |= 1; FIO1DIR = LED1_MASK; T0CTCR = 0; T0MR0 = 500000 - 1; T0MCR = 0x3; VICIntEnable |= (1 << TIMER0_INT); /* Enable Interrupt */ T0TCR = 1; while(1); }