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　/**************************************************************** KPIT Cummins Infosystems Ltd, Pune, India. - 05-Sept-2005. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. *****************************************************************/ #include "inthandler.h" void INT_Dummy(void) __attribute__ ((interrupt_handler)); extern void start (void); /* Startup code (in start.s) */ extern void stack (void); /* stack from linker script */ extern void Manual_Reset_PC (void); /* Manual Reset */ /**---------------------------------- ** Typedef for the function pointer **-----------------------------------*/ typedef void (*fp) (void); #define VECT_SECT __attribute__ ((section (".vects"))) const fp HardwareVectors[] VECT_SECT = { start, /* 0 Power-on reset, Program counter (PC) */ (fp) stack, /* 1 Power-on reset, Stack pointer (SP) */ Manual_Reset_PC, /* 2 Manual Reset, Program counter (PC) */ (fp) stack, /* 3 Manual Reset, Stack pointer (SP) */

　[SH2a-SH7231-Debug] .vects 0 0 1 0x00000000 0 1 0 .vects All files <<FEND>> <<CEND>> <<GEND>> .text 0 0 1 0x0000400 0 0 0 .text All files <<FEND>> 0 .text.* All files <<FEND>> 1 etext <<FEND>> <<CEND>> <<GEND>> .init 0 0 0 0 0 0 .init All files <<FEND>> <<CEND>> <<GEND>> .fini 0 0 0 0 0 0 .fini All files <<FEND>> <<CEND>> <<GEND>> .got 0 0 0 0 0 0 .got All files <<FEND>> 0 .got.plt All files <<FEND>> <<CEND>> <<GEND>> .rodata 0 0 0 0 0 0 .rodata All files <<FEND>> 0 .rodata.* All files <<FEND>> 1 _erodata <<FEND>> <<CEND>> <<GEND>> .eh_frame_hdr 0 0 0 0 0 0 .eh_frame_hdr All files <<FEND>> <<CEND>> <<GEND>> .eh_frame 0 0 0 0 0 0 .eh_frame All files <<FEND>> <<CEND>> <<GEND>> .jcr 0 0 0 0 0 0 .jcr All files <<FEND>> <<CEND>> <<GEND>> .tors 0 0 0 0 0 1 __CTOR_LIST__ <<FEND>> 1 ___ctors <<FEND>> 0 .ctors All files <<FEND>> 1 ___ctors_end <<FEND>> 1 __CTOR_END__ <<FEND>> 1 __DTOR_LIST__ <<FEND>> 1 ___dtors <<FEND>> 0 .dtors All files <<FEND>> 1 ___dtors_end <<FEND>> 1 __DTOR_END__ <<FEND>> 1 _mdata <<FEND>> <<CEND>> <<GEND>> .data 0 0 _mdata 1 0xFFF80000 0 0 1 _data <<FEND>> 0 .data All files <<FEND>> 0 .data.* All files <<FEND>> 1 _edata <<FEND>> <<CEND>> <<GEND>> .gcc_exc 0 0 0 0 0 0 .gcc_exc All files <<FEND>> <<CEND>> <<GEND>> .bss 0 0 0 0 0 1 _bss <<FEND>> 0 .bss All files <<FEND>> 0 .bss.* All files <<FEND>> 0 COMMON All files <<FEND>> 1 _ebss <<FEND>> 1 _end <<FEND>> <<CEND>> <<GEND>> .stack 0 0 1 0xFFF88000 0 0 1 _stack <<FEND>> <<CEND>> <<GEND>> [SH2a-SH7231-Release] .vects 0 0 1 0x00000000 0 1 0 .vects All files <<FEND>> <<CEND>> <<GEND>> .text 0 0 1 0x0000400 0 0 0 .text All files <<FEND>> 0 .text.* All files <<FEND>> 1 etext <<FEND>> <<CEND>> <<GEND>> .init 0 0 0 0 0 0 .init All files <<FEND>> <<CEND>> <<GEND>> .fini 0 0 0 0 0 0 .fini All files <<FEND>> <<CEND>> <<GEND>> .got 0 0 0 0 0 0 .got All files <<FEND>> 0 .got.plt All files <<FEND>> <<CEND>> <<GEND>> .rodata 0 0 0 0 0 0 .rodata All files <<FEND>> 0 .rodata.* All files <<FEND>> 1 _erodata <<FEND>> <<CEND>> <<GEND>> .eh_frame_hdr 0 0 0 0 0 0 .eh_frame_hdr All files <<FEND>> <<CEND>> <<GEND>> .eh_frame 0 0 0 0 0 0 .eh_frame All files <<FEND>> <<CEND>> <<GEND>> .jcr 0 0 0 0 0 0 .jcr All files <<FEND>> <<CEND>> <<GEND>> .tors 0 0 0 0 0 1 __CTOR_LIST__ <<FEND>> 1 ___ctors <<FEND>> 0 .ctors All files <<FEND>> 1 ___ctors_end <<FEND>> 1 __CTOR_END__ <<FEND>> 1 __DTOR_LIST__ <<FEND>> 1 ___dtors <<FEND>> 0 .dtors All files <<FEND>> 1 ___dtors_end <<FEND>> 1 __DTOR_END__ <<FEND>> 1 _mdata <<FEND>> <<CEND>> <<GEND>> .data 0 2 _mdata 1 0xFFF80000 0 0 1 _data <<FEND>> 0 .data All files <<FEND>> 0 .data.* All files <<FEND>> 1 _edata <<FEND>> <<CEND>> <<GEND>> .gcc_exc 0 0 0 0 0 0 .gcc_exc All files <<FEND>> <<CEND>> <<GEND>> .bss 0 0 0 0 0 1 _bss <<FEND>> 0 .bss All files <<FEND>> 0 .bss.* All files <<FEND>> 0 COMMON All files <<FEND>> 1 _ebss <<FEND>> 1 _end <<FEND>> <<CEND>> <<GEND>> .stack 0 0 1 0xFFF88000 0 0 1 _stack <<FEND>> <<CEND>> <<GEND>>

　INT_Illegal_code*0|Reserved 5*INT_Illegal_slot*0|Reserved 7*0|Reserved 8*INT_CPU_Address*INT_DMAC_Address*INT_NMI*INT_User_Break*INT_FPU*INT_HUDI*INT_Bank_Overflow*INT_Bank_Underflow*INT_Divide_by_Zero*INT_Divide_Overflow*0|Reserved 19*0|Reserved 20*0|Reserved 21*0|Reserved 22*0|Reserved 23*0|Reserved 24*0|Reserved 25*0|Reserved 26*INT_FCU*0|Reserved 28*0|Reserved 29*0|Reserved 30*0|Reserved 31*INT_TRAPA32*INT_TRAPA33*INT_TRAPA34*INT_TRAPA35*INT_TRAPA36*INT_TRAPA37*INT_TRAPA38*INT_TRAPA39*INT_TRAPA40*INT_TRAPA41*INT_TRAPA42*INT_TRAPA43*INT_TRAPA44*INT_TRAPA45*INT_TRAPA46*INT_TRAPA47*INT_TRAPA48*INT_TRAPA49*INT_TRAPA50*INT_TRAPA51*INT_TRAPA52*INT_TRAPA53*INT_TRAPA54*INT_TRAPA55*INT_TRAPA56*INT_TRAPA57*INT_TRAPA58*INT_TRAPA59*INT_TRAPA60*INT_TRAPA61*INT_TRAPA62*INT_TRAPA63*INT_IRQ0*INT_IRQ1*INT_IRQ2*INT_IRQ3*INT_IRQ4*INT_IRQ5*INT_IRQ6*INT_IRQ7*INT_IRQ8*INT_IRQ9*INT_IRQ10*INT_IRQ11*INT_IRQ12*INT_IRQ13*INT_IRQ14*INT_IRQ15*INT_IRQ16*INT_IRQ17*INT_IRQ18*INT_IRQ19*INT_IRQ20*INT_IRQ21*INT_IRQ22*INT_IRQ23*INT_TIM32C_CH0D*INT_TIM32C_CH0U*INT_TIM32C_CH1D*INT_TIM32C_CH1U*INT_TIM32C_CH2*0|Reserved 93*0|Reserved 94*INT_KEYC_KSI*0|Reserved 96*0|Reserved 97*0|Reserved 98*0|Reserved 99*0|Reserved 100*0|Reserved 101*0|Reserved 102*0|Reserved 103*INT_AD_ADI0*INT_AD_ADI1*0|Reserved 106*0|Reserved 107*INT_DMAC0_DEI0*INT_DMAC0_HEI0*0|Reserved 110*0|Reserved 111*INT_DMAC1_DEI1*INT_DMAC1_HEI1*0|Reserved 114*0|Reserved 115*INT_DMAC2_DEI2*INT_DMAC2_HEI2*0|Reserved 118*0|Reserved 119*INT_DMAC3_DEI3*INT_DMAC3_HEI3*0|Reserved 122*0|Reserved 123*INT_SCIF_SCIF4_BRF4*INT_SCIF_SCIF4_ERI4*INT_SCIF_SCIF4_RXI4*INT_SCIF_SCIF4_TXI4*INT_SCIF_SCIF5_BRF5*INT_SCIF_SCIF5_ERI5*INT_SCIF_SCIF5_RXI5*INT_SCIF_SCIF5_TXI5*INT_SCIF_SCIF6_BRF6*INT_SCIF_SCIF6_ERI6*INT_SCIF_SCIF6_RXI6*INT_SCIF_SCIF6_TXI6*INT_SCIF_SCIF7_BRF7*INT_SCIF_SCIF7_ERI7*INT_SCIF_SCIF7_RXI7*INT_SCIF_SCIF7_TXI7*INT_CMT_CMI0*INT_CMT_CMI1*INT_CMT2_CM2I*INT_CMT2_IC0I*INT_CMT2_IC1I*INT_CMT2_OC0I*INT_CMT2_OC1I*INT_STB_SSRI*INT_BSC_CMI*INT_RSPI_SPERI*INT_RSPI_SPRXI*INT_RSPI_SPTXI*INT_WDT_ITI*0|Reserved 153*0|Reserved 154*0|Reserved 155*INT_MTU2_MTU0_TGI0A*INT_MTU2_MTU0_TGI0B*INT_MTU2_MTU0_TGI0C*INT_MTU2_MTU0_TGI0D*INT_MTU2_MTU0_TGI0V*INT_MTU2_MTU0_TGI0E*INT_MTU2_MTU0_TGI0F*0|Reserved 163*INT_MTU2_MTU1_TGI1A*INT_MTU2_MTU1_TGI1B*0|Reserved 166*0|Reserved 167*INT_MTU2_MTU1_TGI1V*INT_MTU2_MTU1_TGI1U*0|Reserved 170*0|Reserved 171*INT_MTU2_MTU2_TGI2A*INT_MTU2_MTU2_TGI2B*0|Reserved 174*0|Reserved 175*INT_MTU2_MTU2_TGI2V*INT_MTU2_MTU2_TGI2U*0|Reserved 178*0|Reserved 179*INT_MTU2_MTU3_TGI3A*INT_MTU2_MTU3_TGI3B*INT_MTU2_MTU3_TGI3C*INT_MTU2_MTU3_TGI3D*INT_MTU2_MTU3_TGI3V*0|Reserved 185*0|Reserved 186*0|Reserved 187*INT_MTU2_MTU4_TGI4A*INT_MTU2_MTU4_TGI4B*INT_MTU2_MTU4_TGI4C*INT_MTU2_MTU4_TGI4D*INT_MTU2_MTU4_TGI4V*0|Reserved 193*0|Reserved 194*0|Reserved 195*INT_MTU2_MTU5_TGI5U*INT_MTU2_MTU5_TGI5V*INT_MTU2_MTU5_TGI5W*0|Reserved 199*INT_POE2_OEI1*INT_POE2_OEI2*INT_POE2_OEI3*0|Reserved 203*INT_MTU2S_MTU3S_TGI3A*INT_MTU2S_MTU3S_TGI3B*INT_MTU2S_MTU3S_TGI3C*INT_MTU2S_MTU3S_TGI3D*INT_MTU2S_MTU3S_TGI3V*0|Reserved 209*0|Reserved 210*0|Reserved 211*INT_MTU2S_MTU4S_TGI4A*INT_MTU2S_MTU4S_TGI4B*INT_MTU2S_MTU4S_TGI4C*INT_MTU2S_MTU4S_TGI4D*INT_MTU2S_MTU4S_TGI4V*0|Reserved 217*0|Reserved 218*0|Reserved 219*INT_MTU2S_MTU5S_TGI5U*INT_MTU2S_MTU5S_TGI5V*INT_MTU2S_MTU5S_TGI5W*0|Reserved 223*INT_LVDS_LVOREI*INT_LVDS_LVUREI*INT_LVDS_LVRXI*INT_LVDS_LVECI*INT_IIC3_STPI*INT_IIC3_NAKI*INT_IIC3_RXI*INT_IIC3_TXI*INT_IIC3_TEI*0|Reserved 233*0|Reserved 234*0|Reserved 235*INT_RCANET0_ERS_0*INT_RCANET0_OVR_0*INT_RCANET0_RM01_0*INT_RCANET0_SLE_0*INT_SCI_SCI0_ERI0*INT_SCI_SCI0_RXI0*INT_SCI_SCI0_TXI0*INT_SCI_SCI0_TEI0*INT_SCI_SCI1_ERI1*INT_SCI_SCI1_RXI1*INT_SCI_SCI1_TXI1*INT_SCI_SCI1_TEI1*INT_SCI_SCI2_ERI2*INT_SCI_SCI2_RXI2*INT_SCI_SCI2_TXI2*INT_SCI_SCI2_TEI2*INT_SCI_SCI3_ERI3*INT_SCI_SCI3_RXI3*INT_SCI_SCI3_TXI3*INT_SCI_SCI3_TEI3*