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　/* This is the default Startup for LPC23x devices for the GNU toolchain It has been designed by Raisonance. You can use it, modify it, distribute it freely but without any waranty. ****** (C) COPYRIGHT 2009 RAISONANCE ***** */ .extern main /*; the following are useful for initializing the .data section */ .extern _sidata /*; start address for the initialization values of the .data section. defined in linker script */ .extern _sdata /*; start address for the .data section. defined in linker script */ .extern _edata /*; end address for the .data section. defined in linker script */ /*; the following are useful for initializing the .bss section */ .extern _sbss /*; start address for the .bss section. defined in linker script */ .extern _ebss /*; end address for the .bss section. defined in linker script */ /*; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs*/ /*; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs */ .set Mode_USR, 0x10 /*; User Mode */ .set Mode_FIQ, 0x11 /*; FIQ Mode */ .set Mode_IRQ, 0x12 /*; IRQ Mode */ .set Mode_SVC, 0x13 /*; Supervisor Mode */ .set Mode_ABT, 0x17 /*; Abort Mode */ .set Mode_UNDEF, 0x1B /*; Undefined Mode */ .set Mode_SYS, 0x1F /*; System Mode */ .equ I_Bit, 0x80 /*; when I bit is set, IRQ is disabled*/ .equ F_Bit, 0x40 /*; when F bit is set, FIQ is disabled*/ /*; init value for the stack pointer. defined in linker script */ .extern _estack /*; --- System memory locations */ /*; init value for the stack pointer. defined in linker script */ .extern _estack /*; Stack Sizes. The default values are in the linker script, but they can be overriden. */ .extern _UND_Stack_Init .extern _SVC_Stack_Init .extern _ABT_Stack_Init .extern _FIQ_Stack_Init .extern _IRQ_Stack_Init .extern _USR_Stack_Init .extern _UND_Stack_Size .extern _SVC_Stack_Size .extern _ABT_Stack_Size .extern _FIQ_Stack_Size .extern _IRQ_Stack_Size .extern _USR_Stack_Size SVC_Stack = _SVC_Stack_Init /*_estack*/ /*; 256 byte SVC stack at*/ /*; top of memory */ IRQ_Stack = _IRQ_Stack_Init /*SVC_Stack - 256*/ /*; followed by IRQ stack */ USR_Stack = _USR_Stack_Init /*IRQ_Stack-1024*/ /*; followed by USR stack */ FIQ_Stack = _FIQ_Stack_Init /*USR_Stack-1024*/ /*; followed by FIQ stack*/ ABT_Stack = _ABT_Stack_Init /*FIQ_Stack-256*/ /*; followed by ABT stack */ UNDEF_Stack = _UND_Stack_Init /*ABT_Stack-256*/ /*; followed by UNDEF stack */ /*; --- LPC23xx specific definitions --- */ /*; System Control Block (SCB) Module Definitions*/ .equ SCB_BASE, 0xE01FC000 /*; SCB Base Address*/ .equ PLLCON_OFS, 0x80 /*; PLL Control Offset*/ .equ PLLCFG_OFS, 0x84 /*; PLL Configuration Offset*/ .equ PLLSTAT_OFS, 0x88 /*; PLL Status Offset*/ .equ PLLFEED_OFS, 0x8C /*; PLL Feed Offset*/ .equ CCLKCFG_OFS, 0x104 /*; CPU Clock Divider Reg Offset*/ .equ USBCLKCFG_OFS, 0x108 /*; USB Clock Divider Reg Offset*/ .equ CLKSRCSEL_OFS, 0x10C /*; Clock Source Sel Reg Offset*/ .equ SCS_OFS, 0x1A0 /*; Sys Control and Status Reg Offset*/ .equ PCLKSEL0_OFS, 0x1A8 /*; Periph Clock Sel Reg 0 Offset*/ .equ PCLKSEL1_OFS, 0x1AC /*; Periph Clock Sel Reg 0 Offset*/ /*; Constants*/ .equ OSCRANGE, (1<<4) /*; Oscillator Range Select*/ .equ OSCEN, (1<<5) /*; Main oscillator Enable*/ .equ OSCSTAT, (1<<6) /*; Main Oscillator Status*/ .equ PLLCON_PLLE, (1<<0) /*; PLL Enable*/ .equ PLLCON_PLLC, (1<<1) /*; PLL Connect*/ .equ PLLSTAT_M, (0x7FFF<<0) /*; PLL M Value*/ .equ PLLSTAT_N, (0xFF<<16) /*; PLL N Value*/ .equ PLLSTAT_PLOCK, (1<<26) /*; PLL Lock Status*/ /*; VPBDIV definitions*/ .equ VPBDIV, 0xE01FC100 /*; VPBDIV Address*/ .equ VPBDIV_SETUP, 0 .equ VPBDIV_Val, 0x00000000 .equ PLL_SETUP, 1 .equ CLOCK_SETUP, 1 .equ SCS_Val, 0x00000020 .equ CLKSRCSEL_Val, 0x00000001 .equ PLLCFG_Val, 0x00000007 .equ CCLKCFG_Val, 0x00000003 .equ USBCLKCFG_Val, 0x00000003 .equ PCLKSEL0_Val, 0x00000000 .equ PCLKSEL1_Val, 0x00000000 /*; Memory Accelerator Module (MAM) definitions*/ .equ MAM_BASE, 0xE01FC000 /*; MAM Base Address*/ .equ MAMCR_OFS, 0x00 /*; MAM Control Offset*/ .equ MAMTIM_OFS, 0x04 /*; MAM Timing Offset*/ .equ MAM_SETUP, 1 .equ MAMCR_Val, 0x00000002 .equ MAMTIM_Val, 0x00000004 /* Code Read Protection */ @2012/0813 Modified by SYSLAB .equ CRP1, 0x12345678 .equ CRP2, 0x87654321 .equ CRP3, 0x43218765 .equ NOCRP, 0x11223344 .ifndef NO_CRP .section ".crp_patch","a",%progbits @2012/0813 Modified by SYSLAB .globl CRP_Code CRP_Code: .word NOCRP /* NO CRP Protection*/ .endif /***************************************************************************************/ .globl _start .globl _startup /*.globl End_Handler*/ .section .flash_start,"ax",%progbits _startup: _start: Vectors: ldr PC, =Reset_Handler ldr PC, =UndefinedHandler ldr PC, =SWIHandler ldr PC, =PrefetchAbortHandler ldr PC, =DataAbortHandler nop /*; Vector Checksum Validation */ @ ldr PC, [PC, #-0x0120] /*; Vector from VicVectAddr */ ldr PC, =IRQHandler ldr PC, =FIQHandler /*; Reset Handler*/ @.text Reset_Handler: /*; Setup Stacks */ MSR CPSR_c, #Mode_ABT|F_Bit|I_Bit LDR SP, =ABT_Stack MSR CPSR_c, #Mode_UNDEF|F_Bit|I_Bit LDR SP, =UNDEF_Stack MSR CPSR_c, #Mode_SVC|F_Bit|I_Bit LDR SP, =SVC_Stack MSR CPSR_c, #Mode_FIQ LDR SP, =FIQ_Stack MSR CPSR_c, #Mode_IRQ LDR SP, =IRQ_Stack MSR CPSR_c, #Mode_USR LDR SP, =USR_Stack /* MSR CPSR_c, #Mode_SYS*/ /*; Change to System mode*/ /* ;copy the initial values for .data section from FLASH to RAM */ ldr R1, =_sidata ldr R2, =_sdata ldr R3, =_edata _reset_inidata_loop: cmp R2, R3 ldrlO R0, [R1], #4 strlO R0, [R2], #4 blO _reset_inidata_loop /*; Clear the .bss section */ .if(1) /*;this can be removed for speed as the C standard does not require it*/ mov r0,#0 /*; get a zero */ ldr r1,=_sbss /*; point to bss start */ ldr r2,=_ebss /*; point to bss end */ _reset_inibss_loop: cmp r1,r2 /*; check if some data remains to clear */ strlo r0,[r1],#4 /*; clear 4 bytes */ blo _reset_inibss_loop /*; loop until done */ .endif /*;this can be removed for speed as the C standard does not require it*/ /*; --- Now enter the C code */ b main /*; Note : use B not BL, because an application will*/ /*; never return this way*/ /*; infinite loop after main returns, which should never happen */ loop_after_main: /* b Reset_Handler*/ /*;or maybe you prefer a reset?*/ b loop_after_main /***************************************************************************************/ /*;******************************************************************************* ;* Macro Name : SaveContext ;* Description : This macro used to save the context before entering ; an exception handler. ;* Input : The range of registers to store. ;* Output : none ;*******************************************************************************/ .macro Savecontext $r0,$r12 STMFD sp!,{r0-r12,lr} MRS r1,spsr STMFD sp!,{r1} .endm /*;******************************************************************************* ;* Macro Name : RestoreContext ;* Description : This macro used to restore the context to return from ; an exception handler and continue the program execution. ;* Input : The range of registers to restore. ;* Output : none ;*******************************************************************************/ .macro RestoreContext $r0,$r12 LDMFD sp!,{r1} /*; Restore the saved spsr_mode into r1.*/ MSR spsr_cxsf,r1 /*; Restore spsr_mode.*/ LDMFD sp!,{r0-r12,pc}^ /*; Return to the instruction following...*/ .endm /*; ...the exception interrupt.*/ /*;******************************************************************************* ;* Function Name : FIQHandler ;* Description : This function is called when FIQ ; exception is entered. ;* Input : none ;* Output : none ;******************************************************************************* */ FIQHandler: SUB lr,lr,#4 /*; Update the link register.*/ SaveContext r0,r7 /*; Save the workspace plus the current*/ /*; return address lr_ fiq and spsr_fiq.*/ bl FIQ_Handler /*; Branch to FIQ_Handler.*/ RestoreContext r0,r7 /*; Restore the context and return to the...*/ /*; ...program execution.*/ /*;******************************************************************************* ;* Function Name : UndefinedHandler ;* Description : This function called when undefined instruction ; exception is entered. ;* Input : none ;* Output : none ;*******************************************************************************/ UndefinedHandler: SaveContext r0,r12 /*; Save the workspace plus the current*/ /*; return address lr_ undef and spsr_undef.*/ bl Undefined_Handler /*; Branch to Undefined_Handler.*/ RestoreContext r0,r12 /*; Return to the instruction following..*/ /*; ...the undefined instruction.*/ /*;******************************************************************************* ;* Function Name : SWIHandler ;* Description : This function called when SWI instruction executed. ;* Input : none ;* Output : none ;*******************************************************************************/ SWIHandler: SaveContext r0,r12 /*; Save the workspace plus the current*/ /*; return address lr_ svc and spsr_svc.*/ bl SWI_Handler /*; Branch to SWI_Handler.*/ RestoreContext r0,r12 /*; Return to the instruction following...*/ /*; ...the SWI instruction.*/ /*;******************************************************************************* ;* Function Name : IRQHandler ;* Description : This function called when IRQ exception is entered. ;* Input : none ;* Output : none ;*******************************************************************************/ IRQHandler: SUB lr,lr,#4 /*; Update the link register.*/ SaveContext r0,r12 /*; Save the workspace plus the current*/ /*; return address lr_irq and spsr_irq.*/ bl IRQ_Handler /*; Branch to IRQ_Handler. */ RestoreContext r0,r12 /*; Return to the instruction following that... */ /*; ...has generated the prefetch abort exception.*/ /*;******************************************************************************* ;* Function Name : PrefetchAbortHandler ;* Description : This function called when Prefetch Abort ; exception is entered. ;* Input : none ;* Output : none ;*******************************************************************************/ PrefetchAbortHandler: SUB lr,lr,#4 /*; Update the link register.*/ SaveContext r0,r12 /*; Save the workspace plus the current*/ /*; return address lr_abt and spsr_abt.*/ bl Prefetch_Handler /*; Branch to Prefetch_Handler. */ RestoreContext r0,r12 /*; Return to the instruction following that... */ /*; ...has generated the prefetch abort exception.*/ /*;******************************************************************************* ;* Function Name : DataAbortHandler ;* Description : This function is called when Data Abort ; exception is entered. ;* Input : none ;* Output : none ;********************************************************************************/ DataAbortHandler: SUB lr,lr,#4 /*; Update the link register.*/ SaveContext r0,r12 /*; Save the workspace plus the current*/ /*; return address lr_ abt and spsr_abt.*/ bl Abort_Handler /*; Branch to Abort_Handler.*/ RestoreContext r0,r12 /*; Return to the instruction following that...*/ /*; ...has generated the data abort exception.*/ .weak Undefined_Handler .type Undefined_Handler, %function Undefined_Handler: B . .size Undefined_Handler, . - Undefined_Handler .weak SWI_Handler .type SWI_Handler, %function SWI_Handler: B . .size SWI_Handler, . - SWI_Handler .weak Prefetch_Handler .type Prefetch_Handler, %function Prefetch_Handler: B . .size Prefetch_Handler, . - Prefetch_Handler .weak Abort_Handler .type Abort_Handler, %function Abort_Handler: B . .size Abort_Handler, . - Abort_Handler .weak IRQ_Handler .type IRQ_Handler, %function IRQ_Handler: B . .size IRQ_Handler, . - IRQ_Handler .weak FIQ_Handler .type FIQ_Handler, %function FIQ_Handler: B . .size FIQ_Handler, . - FIQ_Handler /* END OF FILE */ .END

　/* Default secondary/main linker script for Copyright RAISONANCE S.A.S. 2007-2010 !!! This file is automatically generated by Ride if the default linker script option is active !!! Do not modify it if the option is set, as it will be erased at every link. If you need to use your own script please configure your Ride7 project linker options to use your custom linker script You can take this one as example for wrting your custom linker script You can use, copy and distribute this file freely, but without any waranty.*/ /*LPCSubFamilyShort Linker subscript for LPC definitions with 512K Flash and 64K RAM Copyright RAISONANCE 2007-2010 !!! This file is automatically generated by Ride !!! Do not modify it, as it will be erased at every link. You can use, copy and distribute this file freely, but without any waranty. */ /* Memory Spaces Definitions */ MEMORY { RAM (xrw) : ORIGIN = 0x40000000, LENGTH = 0x10000 STARTFLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x1FC CRPPATCH (r) : ORIGIN = 0x1FC, LENGTH = 4 FLASH (rx) : ORIGIN = 0x00000200, LENGTH = 0x7FE00 FLASHPATCH (r) : ORIGIN = 0x0, LENGTH = 0 ENDFLASH (rx) : ORIGIN = 0x0, LENGTH = 0x0 FLASHB1 (rx) : ORIGIN = 0x00000000, LENGTH = 0 EXTMEMB0 (rx) : ORIGIN = 0x00000000, LENGTH = 0 EXTMEMB1 (rx) : ORIGIN = 0x00000000, LENGTH = 0 EXTMEMB2 (rx) : ORIGIN = 0x00000000, LENGTH = 0 EXTMEMB3 (rx) : ORIGIN = 0x00000000, LENGTH = 0 } /* higher address of the user mode stack */ _estack = 0x40010000; /* include the common LPCxxx sub-script */ /* Common part of the linker scripts for ARM7 LPC devices Copyright RAISONANCE 2005 You can use, modify and distribute thisfile freely, but without any waranty. */ /* Registers mapping */ FLASHR_BASE = 0x40100000 ; FLASHPR_BASE = 0x4010DFB0 ; EXTMEM_BASE = 0x60000000 ; RCCU_BASE = 0xA0000000 ; PCU_BASE = 0xA0000040 ; APB1_BASE = 0xC0000000 ; APB2_BASE = 0xE0000000 ; EIC_BASE = 0xFFFFF800 ; PROVIDE( _I2C0 = (APB1_BASE + 0x1000) ); PROVIDE( _I2C1 = (APB1_BASE + 0x2000) ); PROVIDE( _UART0 = (APB1_BASE + 0x4000) ); PROVIDE( _UART1 = (APB1_BASE + 0x5000) ); PROVIDE( _UART2 = (APB1_BASE + 0x6000) ); PROVIDE( _UART3 = (APB1_BASE + 0x7000) ); PROVIDE( _CAN = (APB1_BASE + 0x9000) ); PROVIDE( _BSPI0 = (APB1_BASE + 0xA000) ); PROVIDE( _BSPI1 = (APB1_BASE + 0xB000) ); PROVIDE( _USB = (APB1_BASE + 0x8800) ); PROVIDE( _XTI = (APB2_BASE + 0x101C) ); PROVIDE( _GPIO0 = (APB2_BASE + 0x3000) ); PROVIDE( _GPIO1 = (APB2_BASE + 0x4000) ); PROVIDE( _GPIO2 = (APB2_BASE + 0x5000) ); PROVIDE( _ADC12 = (APB2_BASE + 0x7000) ); PROVIDE( _TIM0 = (APB2_BASE + 0x9000) ); PROVIDE( _TIM1 = (APB2_BASE + 0xA000) ); PROVIDE( _TIM2 = (APB2_BASE + 0xB000) ); PROVIDE( _TIM3 = (APB2_BASE + 0xC000) ); PROVIDE( _RTC = (APB2_BASE + 0xD000) ); PROVIDE( _WDG = (APB2_BASE + 0xE000) ); PROVIDE( _EMI = (EXTMEM_BASE + 0x0C000000) ); PROVIDE( _RCCU = (RCCU_BASE) ); PROVIDE( _PCU = (PCU_BASE) ); /* default stack sizes. These are used by the startup in order to allocate stacks for the different modes. */ __SVC_Stack_Size = 256 ; __IRQ_Stack_Size = 1024 ; __USR_Stack_Size = 1024 ; __FIQ_Stack_Size = 256 ; __ABT_Stack_Size = 256 ; __UND_Stack_Size = 256 ; /*"PROVIDE" allows to easily override these values from an object file or the commmand line.*/ PROVIDE ( _SVC_Stack_Size = __SVC_Stack_Size ) ; PROVIDE ( _IRQ_Stack_Size = __IRQ_Stack_Size ) ; PROVIDE ( _USR_Stack_Size = __USR_Stack_Size ) ; PROVIDE ( _FIQ_Stack_Size = __FIQ_Stack_Size ) ; PROVIDE ( _ABT_Stack_Size = __ABT_Stack_Size ) ; PROVIDE ( _UND_Stack_Size = __UND_Stack_Size ) ; __SVC_Stack_Init = _estack ; __IRQ_Stack_Init = __SVC_Stack_Init - __SVC_Stack_Size ; __USR_Stack_Init = __IRQ_Stack_Init - __IRQ_Stack_Size ; __FIQ_Stack_Init = __USR_Stack_Init - __USR_Stack_Size ; __ABT_Stack_Init = __FIQ_Stack_Init - __FIQ_Stack_Size ; __UND_Stack_Init = __ABT_Stack_Init - __ABT_Stack_Size ; /*"PROVIDE" allows to easily override these values from an object file or the commmand line.*/ PROVIDE ( _SVC_Stack_Init = __SVC_Stack_Init ) ; PROVIDE ( _IRQ_Stack_Init = __IRQ_Stack_Init ) ; PROVIDE ( _USR_Stack_Init = __USR_Stack_Init ) ; PROVIDE ( _FIQ_Stack_Init = __FIQ_Stack_Init ) ; PROVIDE ( _ABT_Stack_Init = __ABT_Stack_Init ) ; PROVIDE ( _UND_Stack_Init = __UND_Stack_Init ) ; /* the user mode stack is an exception because we want it at the end of the RAM. therefore, we just check against a minimum. The value below is the minimum memory required for ALL THE STACKS. There will be a link error if there is not this amount of RAM free at the end. */ _Minimum_Stack_Size = 0xC00 ; /* default ISR addresses. The startup needs these addresses defined from another object file. In case they are not, these PROVIDEs redirect them to the Reset. _start must be defined, usually in the startup. */ PROVIDE( Undefined_Handler = _start ); PROVIDE( SWI_Handler = _start ); PROVIDE( Prefetch_Handler = _start ); PROVIDE( Abort_Handler = _start ); PROVIDE( FIQ_Handler = _start ); PROVIDE( IRQ_Handler = _start ); /* include the sections management sub-script for FLASH mode */ /* Common part of the linker scripts for STR71x devices in FLASH mode (that is, the FLASH is seen at 0) Copyright RAISONANCE 2005 You can use, modify and distribute thisfile freely, but without any waranty. */ /* Sections Definitions */ SECTIONS { /* for Cortex devices, the beginning of the startup code is stored in the .isr_vector section, which goes to FLASH */ .isr_vector : { . = ALIGN(4); KEEP(*(.isr_vector)) /* Startup code */ . = ALIGN(4); } >FLASH /* for Cortex LPC devices, the CRP forces to have a separate region for the vectors at the beginning of the falsh */ .flash_start : { . = ALIGN(4); KEEP(*(.flash_start)) /* vectors */ KEEP(*(.flash_start.*)) /* rest of startup */ . = ALIGN(4); } >STARTFLASH /* for Cortex LPC devices, the CRP contains a code to protect the flash */ .crp_patch : { . = ALIGN(4); KEEP(*(.crp_patch)) /* CRP word */ . = ALIGN(4); } >CRPPATCH /* for some STRx devices, the beginning of the startup code is stored in the .flashtext section, which goes to FLASH */ .flashtext : { . = ALIGN(4); *(.flashtext) /* Startup code */ . = ALIGN(4); } >FLASH /* the program code is stored in the .text section, which goes to Flash */ .text : { . = ALIGN(4); *(.text) /* remaining code */ *(.text.*) /* remaining code */ *(.rodata) /* read-only data (constants) */ *(.rodata*) *(.glue_7) *(.glue_7t) . = ALIGN(4); _etext = .; /* This is used by the startup in order to initialize the .data secion */ _sidata = _etext; } >FLASH /* for some LPC devices, there is a FLASH patch to place at a specified address */ .flashpatch : { . = ALIGN(4); KEEP(*(.flashpatch)) /* flashpatch data */ . = ALIGN(4); } >FLASHPATCH /* for some LPC devices, there is a FLASH patch to place at a specified address and then there is the rest of the flash */ .endflash : { . = ALIGN(4); *(.endflash) /* endflash code */ . = ALIGN(4); _e_endflash = . ; } >ENDFLASH /* This is the initialized data section The program executes knowing that the data is in the RAM but the loader puts the initial values in the FLASH (inidata). It is one task of the startup to copy the initial values from FLASH to RAM. */ .data : AT ( _sidata ) { . = ALIGN(4); /* This is used by the startup in order to initialize the .data secion */ _sdata = . ; _data = . ; *(.data) *(.data.*) *(.RAMtext) . = ALIGN(4); /* This is used by the startup in order to initialize the .data secion */ _edata = . ; } >RAM /*calculate end address of idata*/ _eidata = _sidata + (_edata - _sdata); /*check that idata remains in FLASH region*/ _lastdataromaddress = ORIGIN(FLASH) + LENGTH(FLASH); toobig = ( _eidata > _lastdataromaddress) ? "!!!!!!!!! FLASH IS FULL !!!!!!!!!" : 0 ; /* This is the uninitialized data section */ .bss : { . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _sbss = .; _bss = .; *(.bss) *(COMMON) . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _ebss = . ; } >RAM PROVIDE ( end = _ebss ); PROVIDE ( _end = _ebss ); /* This is the user stack section This is just to check that there is enough RAM left for the User mode stack It should generate an error if it's full. */ ._usrstack : { . = ALIGN(4); _susrstack = . ; . = . + _Minimum_Stack_Size ; . = ALIGN(4); _eusrstack = . ; } >RAM /* this is the FLASH Bank1 */ /* the C or assembly source must explicitly place the code or data there using the "section" attribute */ .b1text : { *(.b1text) /* remaining code */ *(.b1rodata) /* read-only data (constants) */ *(.b1rodata*) } >FLASHB1 /* this is the EXTMEM */ /* the C or assembly source must explicitly place the code or data there using the "section" attribute */ /* EXTMEM Bank0 */ .eb0text : { *(.eb0text) /* remaining code */ *(.eb0rodata) /* read-only data (constants) */ *(.eb0rodata*) } >EXTMEMB0 /* EXTMEM Bank1 */ .eb1text : { *(.eb1text) /* remaining code */ *(.eb1rodata) /* read-only data (constants) */ *(.eb1rodata*) } >EXTMEMB1 /* EXTMEM Bank2 */ .eb2text : { *(.eb2text) /* remaining code */ *(.eb2rodata) /* read-only data (constants) */ *(.eb2rodata*) } >EXTMEMB2 /* EXTMEM Bank0 */ .eb3text : { *(.eb3text) /* remaining code */ *(.eb3rodata) /* read-only data (constants) */ *(.eb3rodata*) } >EXTMEMB3 __exidx_start = .; __exidx_end = .; /* after that it's only debugging information. */ /* remove the debugging information from the standard libraries */ /DISCARD/ : { libc.a ( * ) libm.a ( * ) libgcc.a ( * ) } /* Stabs debugging sections. */ .stab 0 : { *(.stab) } .stabstr 0 : { *(.stabstr) } .stab.excl 0 : { *(.stab.excl) } .stab.exclstr 0 : { *(.stab.exclstr) } .stab.index 0 : { *(.stab.index) } .stab.indexstr 0 : { *(.stab.indexstr) } .comment 0 : { *(.comment) } /* DWARF debug sections. Symbols in the DWARF debugging sections are relative to the beginning of the section so we begin them at 0. */ /* DWARF 1 */ .debug 0 : { *(.debug) } .line 0 : { *(.line) } /* GNU DWARF 1 extensions */ .debug_srcinfo 0 : { *(.debug_srcinfo) } .debug_sfnames 0 : { *(.debug_sfnames) } /* DWARF 1.1 and DWARF 2 */ .debug_aranges 0 : { *(.debug_aranges) } .debug_pubnames 0 : { *(.debug_pubnames) } /* DWARF 2 */ .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } .debug_abbrev 0 : { *(.debug_abbrev) } .debug_line 0 : { *(.debug_line) } .debug_frame 0 : { *(.debug_frame) } .debug_str 0 : { *(.debug_str) } .debug_loc 0 : { *(.debug_loc) } .debug_macinfo 0 : { *(.debug_macinfo) } /* SGI/MIPS DWARF 2 extensions */ .debug_weaknames 0 : { *(.debug_weaknames) } .debug_funcnames 0 : { *(.debug_funcnames) } .debug_typenames 0 : { *(.debug_typenames) } .debug_varnames 0 : { *(.debug_varnames) } }

　 //handle start of flash trick for LPC1x CRP thing if ( (LPCSubFamilyShort == "LPC18") || (LPCSubFamilyShort == "LPC17") || (LPCSubFamilyShort == "LPC13") || (LPCSubFamilyShort == "LPC12" || (LPCSubFamilyShort == "LPC11") ) { Device_FlashStartSize = 0x2FC; } //handle start of flash trick for LPC2x CRP thing if ( (LPCSubFamilyShort == "LPC21") || (LPCSubFamilyShort == "LPC22") || (LPCSubFamilyShort == "LPC23") || (LPCSubFamilyShort == "LPC24") ) { Device_FlashStartSize = 0x1FC; } ・ ・ ・ //for LPC1x, we must split the Flash in two parts and add a CRP word at 0x2FC. if ( (LPCSubFamilyShort == "LPC18") || (LPCSubFamilyShort == "LPC17") || (LPCSubFamilyShort == "LPC13") || (LPCSubFamilyShort == "LPC12" || (LPCSubFamilyShort == "LPC11") ) { var LPC_FlashPatchAddr2 = LPC_FlashPatchAddr ; file2.Write (" CRPPATCH (r) : ORIGIN = 0x2FC, LENGTH = 4\n"); } else if ( (LPCSubFamilyShort == "LPC21") || (LPCSubFamilyShort == "LPC22") || (LPCSubFamilyShort == "LPC23") || (LPCSubFamilyShort == "LPC24") ) { var LPC_FlashPatchAddr2 = LPC_FlashPatchAddr ; file2.Write (" CRPPATCH (r) : ORIGIN = 0x1FC, LENGTH = 4\n"); } ・ ・ ・