KPIT GNU Tools (14) GNUSH v1001 Windows Tool Chain (ELF): SYSLAB blog

KPIT GNU Tools (14) GNUSH v1001 Windows Tool Chain (ELF) ― 2010年04月23日 23時23分35秒

Kpit GNUSH v1001 Windows Tool Chain Project Generator

Kpit GNUSH v1001 Windows Tool Chain (ELF) に
SH7216 SH7262 SH7264 を追加した。

これで FRK-SH2A の準備は完了だ。

でも、Renesas の環境を使えば何の問題もないのだけど．．．

これは SH7216 の場合

C:\Program Files\Renesas\Hew\System\Pg\KPIT GNUSH-ELF\GNUSH_Info\Support_3\scapp.det
C:\Program Files\Renesas\Hew\System\Pg\KPIT GNUSH-ELF\GNUSH_Info\Support_3\scppapp.det
C:\Program Files\Renesas\Hew\System\Pg\KPIT GNUSH-ELF\GNUSH_Info\Support_3\SH-2A\SH7216.PGD
C:\Program Files\Renesas\Hew\System\Pg\KPIT GNUSH-ELF\GNUSH_Info\Generate\hwsetup\7216.c
C:\Program Files\Renesas\Hew\System\Pg\KPIT GNUSH-ELF\GNUSH_Info\Generate\IntPRG\SH7216.c
C:\Program Files\Renesas\Hew\System\Pg\KPIT GNUSH-ELF\GNUSH_Info\Generate\iodefine\7216.h
C:\Program Files\Renesas\Hew\System\Pg\KPIT GNUSH-ELF\GNUSH_Info\Generate\vect\SH7216.h
C:\Program Files\Renesas\Hew\System\Pg\KPIT GNUSH-ELF\GNUSH_Info\Generate\VECTTBL\SH7216.c
C:\Program Files\Renesas\Hew\System\Pg\KPIT GNUSH-ELF\Hardware\SH-2A\SH7216.dat

まず、scapp.det と scppapp.det 、これらは同じ内容でリンカースクリプトの集合体だ。
追加するデバイスのリンカースクリプト情報を書き加える。
以下は、SH7216 の例だ。

　　[SH2a-SH7216] .vects|0|0||1|0x00000000|0|1|0|.vects|All-files|<<FEND>>|<<CEND>>|<<GEND>>|.text|0|0||1|0x0000400|0|0|0|.text|All-files|<<FEND>>|0|.text.*|All-files|<<FEND>>|1|etext|<<FEND>>|<<CEND>>|<<GEND>>|.init|0|0||0||0|0|0|.init|All-files|<<FEND>>|<<CEND>>|<<GEND>>|.fini|0|0||0||0|0|0|.fini|All-files|<<FEND>>|<<CEND>>|<<GEND>>|.got|0|0||0||0|0|0|.got|All-files|<<FEND>>|0|.got.plt|All-files|<<FEND>>|<<CEND>>|<<GEND>>|.rodata|0|0||0||0|0|0|.rodata|All-files|<<FEND>>|0|.rodata.*|All-files|<<FEND>>|1|_erodata|<<FEND>>|<<CEND>>|<<GEND>>|.eh_frame_hdr|0|0||0||0|0|0|.eh_frame_hdr|All-files|<<FEND>>|<<CEND>>|<<GEND>>|.eh_frame|0|0||0||0|0|0|.eh_frame|All-files|<<FEND>>|<<CEND>>|<<GEND>>|.jcr|0|0||0||0|0|0|.jcr|All-files|<<FEND>>|<<CEND>>|<<GEND>>|.tors|0|0||0||0|0|1|__CTOR_LIST__|<<FEND>>|1|___ctors|<<FEND>>|0|.ctors|All-files|<<FEND>>|1|___ctors_end|<<FEND>>|1|__CTOR_END__|<<FEND>>|1|__DTOR_LIST__|<<FEND>>|1|___dtors|<<FEND>>|0|.dtors|All-files|<<FEND>>|1|___dtors_end|<<FEND>>|1|__DTOR_END__|<<FEND>>|1|_mdata|<<FEND>>|<<CEND>>|<<GEND>>|.data|0|2|_mdata|1|0xFFF80000|0|0|1|_data|<<FEND>>|0|.data|All-files|<<FEND>>|0|.data.*|All-files|<<FEND>>|1|_edata|<<FEND>>|<<CEND>>|<<GEND>>|.gcc_exc|0|0||0||0|0|0|.gcc_exc|All-files|<<FEND>>|<<CEND>>|<<GEND>>|.bss|0|0||0||0|0|1|_bss|<<FEND>>|0|.bss|All-files|<<FEND>>|0|.bss.*|All-files|<<FEND>>|0|COMMON|All-files|<<FEND>>|1|_ebss|<<FEND>>|1|_end|<<FEND>>|<<CEND>>|<<GEND>>|.stack|0|0||1|0xFFF90000|0|0|1|_stack|<<FEND>>|<<CEND>>|<<GEND>>

次に SH7216.PGD 、プロジェクトジェネレータ・データファイルでプロジェクトに含めるファイルやセクション情報を記述する。

　　2007.02 [Files] 1=resetprg\SH2A.asm 2=1 3=DBsct\sh.c 4=IntPRG\SH7216.c 5=vecttbl\SH7216.c 6=lowlvl\sh.src 7=lowsrc\sh.c 8=sbrk\sh.c 9=iodefine\7216.h 10=vect\SH7216.h 11=hwsetup\7216.c 12=0 13=0 14=0 15=1 16=1 17=Common\Main.c 18=Common\typedefine.h 19=Common\intrinsics.h Asm 11=hwsetup\sh.src Demo 17=Common\Sort.c [CPU Type Data] I/O Stream=20 Heap Size=H'400 Hw Setup Function=HardwareSetup Stack Pointer=H'FFF90000 Stack Size=H'400 Summary 0= Summary 1= Summary 2=\n Summary 3=Program start H'400. Summary 4=RAM start H'FFF80000. Summary 5=This base is the SH-2A FPU. [Section] Reset Section= Reset Address= Vector Section=.vects Vector Address=000000000 ResetPRG Section=PResetPRG,PIntPRG ResetPRG Address=000000400 Program Section=.text,.rodata Program Address=000000800 B Section=.data,.bss B Address=0FFF80000 Stack Section=.stack Stack Address=FFF90000 [C++ Section] Reset Section= Reset Address= Vector Section=.vects Vector Address=000000000 ResetPRG Section=PResetPRG,PIntPRG ResetPRG Address=000000400 Program Section=.text,.rodata Program Address=000000800 B Section=.data,.bss B Address=0FFF80000 Stack Section=.stack Stack Address=FFF90000 [Option] Compiler= Assembler= OptLinker= Converter= Librarian=

hwsetup￥7216.c は start.asm から呼び出される初期化関数だ。（文字がない部分もコピーして張り付ける）

　　 /********************************************************************* * * Device : SH2A-FPU/SH7216 * * File Name : hwsetup.c(.cpp) * * Abstract : Hardware Setup file. * * History : 1.00 (2009-04-28) [Hardware Manual Revision : 1.01] * * NOTE : THIS IS A TYPICAL EXAMPLE. * * Copyright(c) 2009 Renesas Technology Corp. * And Renesas Solutions Corp.,All Rights Reserved. * *********************************************************************/ #include "iodefine.h" #ifdef __cplusplus extern "C" { #endif extern void hw_initialise(void); #ifdef __cplusplus } #endif void hw_initialise(void) { /* BSC.CMNCR.LONG = 0xFFFFFFFF; BSC.CS0BCR.LONG = 0xFFFFFFFF; BSC.CS1BCR.LONG = 0xFFFFFFFF; BSC.CS2BCR.LONG = 0xFFFFFFFF; BSC.CS3BCR.LONG = 0xFFFFFFFF; BSC.CS4BCR.LONG = 0xFFFFFFFF; BSC.CS5BCR.LONG = 0xFFFFFFFF; BSC.CS6BCR.LONG = 0xFFFFFFFF; BSC.CS7BCR.LONG = 0xFFFFFFFF; */ }

IntPRG￥SH7216.c は割り込みプログラム。もちろん中身は空。（文字がない部分もコピーして張り付ける）

　　 /********************************************************************* * * Device : SH2A-FPU/SH7216 * * File Name : intprg.c * * Abstract : Interrupt Program. * * History : 1.00 (2009-04-28) [Hardware Manual Revision : 1.01] * * NOTE : THIS IS A TYPICAL EXAMPLE. * * Copyright(c) 2008 Renesas Technology Corp. * And Renesas Solutions Corp.,All Rights Reserved. * *********************************************************************/ #include "inthandler.h" //;2 Manual Reset PC void Manual_Reset_PC(void){/* sleep(); */} // 3 Manual Reset SP // 4 Illegal code void INT_Illegal_code(void){/* sleep(); */} // 5 Reserved // 6 Illegal slot void INT_Illegal_slot(void){/* sleep(); */} // 7 Reserved // 8 Reserved // 9 CPU Address error void INT_CPU_Address(void){/* sleep(); */} // 10 DMAC Address erro void INT_DMAC_Address(void){/* sleep(); */} // 11 NMI void INT_NMI(void){/* sleep(); */} // 12 User breakpoint trap void INT_User_Break(void){/* sleep(); */} // 13 INT_FPU void INT_FPU(void){/* sleep(); */} // 14 H-UDI void INT_HUDI(void){/* sleep(); */} // 15 Bank Overflow void INT_Bank_Overflow(void){/* sleep(); */} // 16 Bank Underflow void INT_Bank_Underflow(void){/* sleep(); */} // 17 Divide by zero void INT_Divide_by_Zero(void){/* sleep(); */} // 18 Divide Overflow void INT_Divide_Overflow(void){/* sleep(); */} // 19 Reserved // 20 Reserved // 21 Reserved // 22 Reserved // 23 Reserved // 24 Reserved // 25 Reserved // 26 Reserved // 27 Reserved // 28 Reserved // 29 Reserved // 30 Reserved // 31 Reserved // 32 TRAPA (User Vector) void INT_TRAPA32(void){/* sleep(); */} // 33 TRAPA (User Vector) void INT_TRAPA33(void){/* sleep(); */} // 34 TRAPA (User Vector) void INT_TRAPA34(void){/* sleep(); */} // 35 TRAPA (User Vector) void INT_TRAPA35(void){/* sleep(); */} // 36 TRAPA (User Vector) void INT_TRAPA36(void){/* sleep(); */} // 37 TRAPA (User Vector) void INT_TRAPA37(void){/* sleep(); */} // 38 TRAPA (User Vector) void INT_TRAPA38(void){/* sleep(); */} // 39 TRAPA (User Vector) void INT_TRAPA39(void){/* sleep(); */} // 40 TRAPA (User Vector) void INT_TRAPA40(void){/* sleep(); */} // 41 TRAPA (User Vector) void INT_TRAPA41(void){/* sleep(); */} // 42 TRAPA (User Vector) void INT_TRAPA42(void){/* sleep(); */} // 43 TRAPA (User Vector) void INT_TRAPA43(void){/* sleep(); */} // 44 TRAPA (User Vector) void INT_TRAPA44(void){/* sleep(); */} // 45 TRAPA (User Vector) void INT_TRAPA45(void){/* sleep(); */} // 46 TRAPA (User Vector) void INT_TRAPA46(void){/* sleep(); */} // 47 TRAPA (User Vector) void INT_TRAPA47(void){/* sleep(); */} // 48 TRAPA (User Vector) void INT_TRAPA48(void){/* sleep(); */} // 49 TRAPA (User Vector) void INT_TRAPA49(void){/* sleep(); */} // 50 TRAPA (User Vector) void INT_TRAPA50(void){/* sleep(); */} // 51 TRAPA (User Vector) void INT_TRAPA51(void){/* sleep(); */} // 52 TRAPA (User Vector) void INT_TRAPA52(void){/* sleep(); */} // 53 TRAPA (User Vector) void INT_TRAPA53(void){/* sleep(); */} // 54 TRAPA (User Vector) void INT_TRAPA54(void){/* sleep(); */} // 55 TRAPA (User Vector) void INT_TRAPA55(void){/* sleep(); */} // 56 TRAPA (User Vector) void INT_TRAPA56(void){/* sleep(); */} // 57 TRAPA (User Vector) void INT_TRAPA57(void){/* sleep(); */} // 58 TRAPA (User Vector) void INT_TRAPA58(void){/* sleep(); */} // 59 TRAPA (User Vector) void INT_TRAPA59(void){/* sleep(); */} // 60 TRAPA (User Vector) void INT_TRAPA60(void){/* sleep(); */} // 61 TRAPA (User Vector) void INT_TRAPA61(void){/* sleep(); */} // 62 TRAPA (User Vector) void INT_TRAPA62(void){/* sleep(); */} // 63 TRAPA (User Vector) void INT_TRAPA63(void){/* sleep(); */} // 64 Interrupt IRQ0 void INT_IRQ0(void){/* sleep(); */} // 65 Interrupt IRQ1 void INT_IRQ1(void){/* sleep(); */} // 66 Interrupt IRQ2 void INT_IRQ2(void){/* sleep(); */} // 67 Interrupt IRQ3 void INT_IRQ3(void){/* sleep(); */} // 68 Interrupt IRQ4 void INT_IRQ4(void){/* sleep(); */} // 69 Interrupt IRQ5 void INT_IRQ5(void){/* sleep(); */} // 70 Interrupt IRQ6 void INT_IRQ6(void){/* sleep(); */} // 71 Interrupt IRQ7 void INT_IRQ7(void){/* sleep(); */} // 72 Reserved // 73 Reserved // 74 Reserved // 75 Reserved // 76 Reserved // 77 Reserved // 78 Reserved // 79 Reserved // 80 Reserved // 81 Reserved // 82 Reserved // 83 Reserved // 84 Reserved // 85 Reserved // 86 Reserved // 87 Reserved // 88 Reserved // 89 Reserved // 90 Reserved // 91 ROMFLD FIFE void INT_ROMFLD_FIFE(void){/* sleep(); */} // 92 ADC ADI0 void INT_ADC_ADI0(void){/* sleep(); */} // 93 Reserved // 94 Reserved // 95 Reserved // 96 ADC ADI1 void INT_ADC_ADI1(void){/* sleep(); */} // 97 Reserved // 98 Reserved // 99 Reserved // 100 Reserved // 101 Reserved // 102 Reserved // 103 Reserved // 104 RCAN ERS0 void INT_RCAN_ERS0(void){/* sleep(); */} // 105 RCAN OVR0 void INT_RCAN_OVR0(void){/* sleep(); */} // 106 RCAN RM00 RM10 void INT_RCAN_RM00_RM10(void){/* sleep(); */} // 107 RCAN SLE0 void INT_SLE0(void){/* sleep(); */} // 108 DMAC0 DEI void INT_DMAC0_DEI0(void){/* sleep(); */} // 109 DMAC0 HEI void INT_DMAC0_HEI0(void){/* sleep(); */} // 110 Reserved // 111 Reserved // 112 DMAC1 DEI void INT_DMAC1_DEI1(void){/* sleep(); */} // 113 DMAC1 HEI void INT_DMAC1_HEI1(void){/* sleep(); */} // 114 Reserved // 115 Reserved // 116 DMAC2 DEI void INT_DMAC2_DEI2(void){/* sleep(); */} // 117 DMAC2 HEI void INT_DMAC2_HEI2(void){/* sleep(); */} // 118 Reserved // 119 Reserved // 120 DMAC3 DEI void INT_DMAC3_DEI3(void){/* sleep(); */} // 121 DMAC3 HEI void INT_DMAC3_HEI3(void){/* sleep(); */} // 122 Reserved // 123 Reserved // 124 DMAC4 DEI void INT_DMAC4_DEI4(void){/* sleep(); */} // 125 DMAC4 HEI void INT_DMAC4_HEI4(void){/* sleep(); */} // 126 Reserved // 127 Reserved // 128 DMAC5 DEI void INT_DMAC5_DEI5(void){/* sleep(); */} // 129 DMAC5 HEI void INT_DMAC5_HEI5(void){/* sleep(); */} // 130 Reserved // 131 Reserved // 132 DMAC6 DEI void INT_DMAC6_DEI6(void){/* sleep(); */} // 133 DMAC6 HEI void INT_DMAC6_HEI6(void){/* sleep(); */} // 134 Reserved // 135 Reserved // 136 DMAC7 DEI void INT_DMAC7_DEI7(void){/* sleep(); */} // 137 DMAC7 HEI void INT_DMAC7_HEI7(void){/* sleep(); */} // 138 Reserved // 139 Reserved // 140 CMT CMI0 void INT_CMT_CMI0(void){/* sleep(); */} // 141 Reserved // 142 Reserved // 143 Reserved // 144 CMT CMI1 void INT_CMT_CMI1(void){/* sleep(); */} // 145 Reserved // 146 Reserved // 147 Reserved // 148 BSC CMI void INT_BSC_CMI(void){/* sleep(); */} // 149 Reserved // 150 USB USBRXI1 void INT_USB_USBRXI1(void){/* sleep(); */} // 151 USB USBTXI1 void INT_USB_USBTXI1(void){/* sleep(); */} // 152 WDT ITI void INT_WDT_ITI(void){/* sleep(); */} // 153 ETHERC EINT0 void INT_ETHERC_EINT0(void){/* sleep(); */} // 154 USB USBRXI0 void INT_USB_USBRXI0(void){/* sleep(); */} // 155 USB USBTXI0 void INT_USB_USBTXI0(void){/* sleep(); */} // 156 MTU20 TGIA0 void INT_MTU20_TGIA0(void){/* sleep(); */} // 157 MTU20 TGIB0 void INT_MTU20_TGIB0(void){/* sleep(); */} // 158 MTU20 TGIC0 void INT_MTU20_TGIC0(void){/* sleep(); */} // 159 MTU20 TGID0 void INT_MTU20_TGID0(void){/* sleep(); */} // 160 MTU20 TCIV0 void INT_MTU20_TCIV0(void){/* sleep(); */} // 161 MTU20 TGIE0 void INT_MTU20_TGIE0(void){/* sleep(); */} // 162 MTU20 TGIF0 void INT_MTU20_TGIF0(void){/* sleep(); */} // 163 Reserved // 164 MTU21 TGIA1 void INT_MTU21_TGIA1(void){/* sleep(); */} // 165 MTU21 TGIB1 void INT_MTU21_TGIB1(void){/* sleep(); */} // 166 Reserved // 167 Reserved // 168 MTU21 TCIV1 void INT_MTU21_TCIV1(void){/* sleep(); */} // 169 MTU21 TCIU1 void INT_MTU21_TCIU1(void){/* sleep(); */} // 170 Reserved // 171 Reserved // 172 MTU22 TGIA2 void INT_MTU22_TGIA2(void){/* sleep(); */} // 173 MTU22 TGIB2 void INT_MTU22_TGIB2(void){/* sleep(); */} // 174 Reserved // 175 Reserved // 176 MTU22 TCIV2 void INT_MTU22_TCIV2(void){/* sleep(); */} // 177 MTU22 TCIU2 void INT_MTU22_TCIU2(void){/* sleep(); */} // 178 Reserved // 179 Reserved // 180 MTU23 TGIA3 void INT_MTU23_TGIA3(void){/* sleep(); */} // 181 MTU23 TGIB3 void INT_MTU23_TGIB3(void){/* sleep(); */} // 182 MTU23 TGIC3 void INT_MTU23_TGIC3(void){/* sleep(); */} // 183 MTU23 TGID3 void INT_MTU23_TGID3(void){/* sleep(); */} // 184 MTU23 TCIV3 void INT_MTU23_TCIV3(void){/* sleep(); */} // 185 Reserved // 186 Reserved // 187 Reserved // 188 MTU24 TGIA4 void INT_MTU24_TGIA4(void){/* sleep(); */} // 189 MTU24 TGIB4 void INT_MTU24_TGIB4(void){/* sleep(); */} // 190 MTU24 TGIC4 void INT_MTU24_TGIC4(void){/* sleep(); */} // 191 MTU24 TGID4 void INT_MTU24_TGID4(void){/* sleep(); */} // 192 MTU24 TCIV4 void INT_MTU24_TCIV4(void){/* sleep(); */} // 193 Reserved // 194 Reserved // 195 Reserved // 196 MTU25 TGIU5 void INT_MTU25_TGIU5(void){/* sleep(); */} // 197 MTU25 TGIV5 void INT_MTU25_TGIV5(void){/* sleep(); */} // 198 MTU25 TGIW5 void INT_MTU25_TGIW5(void){/* sleep(); */} // 199 Reserved // 200 POE2 OEI1 void INT_POE2_OEI1(void){/* sleep(); */} // 201 POE2 OEI2 void INT_POE2_OEI2(void){/* sleep(); */} // 202 Reserved // 203 Reserved // 204 MTU2S3 TGIA3S void INT_MTU2S3_TGIA3S(void){/* sleep(); */} // 205 MTU2S3 TGIB3S void INT_MTU2S3_TGIB3S(void){/* sleep(); */} // 206 MTU2S3 TGIC3S void INT_MTU2S3_TGIC3S(void){/* sleep(); */} // 207 MTU2S3 TGID3S void INT_MTU2S3_TGID3S(void){/* sleep(); */} // 208 MTU2S3 TCIV3S void INT_MTU2S3_TCIV3S(void){/* sleep(); */} // 209 Reserved // 210 Reserved // 211 Reserved // 212 MTU2S4 TGIA4S void INT_MTU2S4_TGIA4S(void){/* sleep(); */} // 213 MTU2S4 TGIB4S void INT_MTU2S4_TGIB4S(void){/* sleep(); */} // 214 MTU2S4 TGIC4S void INT_MTU2S4_TGIC4S(void){/* sleep(); */} // 215 MTU2S4 TGID4S void INT_MTU2S4_TGID4S(void){/* sleep(); */} // 216 MTU2S4 TCIV4S void INT_MTU2S4_TCIV4S(void){/* sleep(); */} // 217 Reserved // 218 Reserved // 219 Reserved // 220 MTU2S5 TGIU5S void INT_MTU2S5_TGIU5S(void){/* sleep(); */} // 221 MTU2S5 TGIV5S void INT_MTU2S5_TGIV5S(void){/* sleep(); */} // 222 MTU2S5 TGIW5S void INT_MTU2S5_TGIW5S(void){/* sleep(); */} // 223 Reserved // 224 POE2 OEI3 void INT_POE2_OEI3(void){/* sleep(); */} // 225 Reserved // 226 USB USI0 void INT_USB_USI0(void){/* sleep(); */} // 227 USB USI1 void INT_USB_USI1(void){/* sleep(); */} // 228 IIC3 STPI void INT_IIC3_STPI(void){/* sleep(); */} // 229 IIC3 NAKI void INT_IIC3_NAKI(void){/* sleep(); */} // 230 IIC3 RXI void INT_IIC3_RXI(void){/* sleep(); */} // 231 IIC3 TXI void INT_IIC3_TXI(void){/* sleep(); */} // 232 IIC3 TEI void INT_IIC3_TEI(void){/* sleep(); */} // 233 RSPI SPEI void INT_RSPI_SPEI(void){/* sleep(); */} // 234 RSPI SPRI void INT_RSPI_SPRI(void){/* sleep(); */} // 235 RSPI SPTI void INT_RSPI_SPTI(void){/* sleep(); */} // 236 SCI SCI4 ERI4 void INT_SCI_SCI4_ERI4(void){/* sleep(); */} // 237 SCI SCI4 RXI4 void INT_SCI_SCI4_RXI4(void){/* sleep(); */} // 238 SCI SCI4 TXI4 void INT_SCI_SCI4_TXI4(void){/* sleep(); */} // 239 SCI SCI4 TEI4 void INT_SCI_SCI4_TEI4(void){/* sleep(); */} // 240 SCI SCI0 ERI0 void INT_SCI_SCI0_ERI0(void){/* sleep(); */} // 241 SCI SCI0 RXI0 void INT_SCI_SCI0_RXI0(void){/* sleep(); */} // 242 SCI SCI0 TXI0 void INT_SCI_SCI0_TXI0(void){/* sleep(); */} // 243 SCI SCI0 TEI0 void INT_SCI_SCI0_TEI0(void){/* sleep(); */} // 244 SCI SCI1 ERI1 void INT_SCI_SCI1_ERI1(void){/* sleep(); */} // 245 SCI SCI1 RXI1 void INT_SCI_SCI1_RXI1(void){/* sleep(); */} // 246 SCI SCI1 TXI1 void INT_SCI_SCI1_TXI1(void){/* sleep(); */} // 247 SCI SCI1 TEI1 void INT_SCI_SCI1_TEI1(void){/* sleep(); */} // 248 SCI SCI2 ERI2 void INT_SCI_SCI2_ERI2(void){/* sleep(); */} // 249 SCI SCI2 RXI2 void INT_SCI_SCI2_RXI2(void){/* sleep(); */} // 250 SCI SCI2 TXI2 void INT_SCI_SCI2_TXI2(void){/* sleep(); */} // 251 SCI SCI2 TEI2 void INT_SCI_SCI2_TEI2(void){/* sleep(); */} // 252 SCIF SCIF3 BRI3 void INT_SCIF_SCIF3_BRI3(void){/* sleep(); */} // 253 SCIF SCIF3 ERI3 void INT_SCIF_SCIF3_ERI3(void){/* sleep(); */} // 254 SCIF SCIF3 RXI3 void INT_SCIF_SCIF3_RXI3(void){/* sleep(); */} // 255 SCIF SCIF3 TXI3 void INT_SCIF_SCIF3_TXI3(void){/* sleep(); */} // Dummy void INT_Dummy(void){/* sleep(); */}

iodefine￥7216.h ご存じのとおりＩ／Ｏヘッダーファイル Renesas のものがそのまま使える。
vect￥SH7216.h ベクター定義ヘッダー（文字がない部分もコピーして張り付ける）

　　 /********************************************************************* * * Device : SH2A-FPU/SH7216 * * File Name : vect.h * * Abstract : Definition of Vector. * * History : 1.00 (2009-04-28) [Hardware Manual Revision : 1.01] * * NOTE : THIS IS A TYPICAL EXAMPLE. * * Copyright(c) 2009 Renesas Technology Corp. * And Renesas Solutions Corp.,All Rights Reserved. * *********************************************************************/ #ifndef VECT_H #define VECT_H //;<<VECTOR DATA START (POWER ON RESET)>> //;0 Power On Reset PC //;<<VECTOR DATA END (POWER ON RESET)>> // 1 Power On Reset SP //;<<VECTOR DATA START (MANUAL RESET)>> //;2 Manual Reset PC void Manual_Reset_PC(void); //;<<VECTOR DATA END (MANUAL RESET)>> // 3 Manual Reset SP // 4 Illegal code void INT_Illegal_code(void) __attribute__ ((interrupt_handler)); // 5 Reserved // 6 Illegal slot void INT_Illegal_slot(void) __attribute__ ((interrupt_handler)); // 7 Reserved // 8 Reserved // 9 CPU Address error void INT_CPU_Address(void) __attribute__ ((interrupt_handler)); // 10 DMAC Address erro void INT_DMAC_Address(void) __attribute__ ((interrupt_handler)); // 11 NMI void INT_NMI(void) __attribute__ ((interrupt_handler)); // 12 User breakpoint trap void INT_User_Break(void) __attribute__ ((interrupt_handler)); // 13 INT_FPU void INT_FPU(void) __attribute__ ((interrupt_handler)); // 14 H-UDI void INT_HUDI(void) __attribute__ ((interrupt_handler)); // 15 Bank Overflow void INT_Bank_Overflow(void) __attribute__ ((interrupt_handler)); // 16 Bank Underflow void INT_Bank_Underflow(void) __attribute__ ((interrupt_handler)); // 17 Divide by zero void INT_Divide_by_Zero(void) __attribute__ ((interrupt_handler)); // 18 Divide Overflow void INT_Divide_Overflow(void) __attribute__ ((interrupt_handler)); // 19 Reserved // 20 Reserved // 21 Reserved // 22 Reserved // 23 Reserved // 24 Reserved // 25 Reserved // 26 Reserved // 27 Reserved // 28 Reserved // 29 Reserved // 30 Reserved // 31 Reserved // 32 TRAPA (User Vector) void INT_TRAPA32(void) __attribute__ ((interrupt_handler)); // 33 TRAPA (User Vector) void INT_TRAPA33(void) __attribute__ ((interrupt_handler)); // 34 TRAPA (User Vector) void INT_TRAPA34(void) __attribute__ ((interrupt_handler)); // 35 TRAPA (User Vector) void INT_TRAPA35(void) __attribute__ ((interrupt_handler)); // 36 TRAPA (User Vector) void INT_TRAPA36(void) __attribute__ ((interrupt_handler)); // 37 TRAPA (User Vector) void INT_TRAPA37(void) __attribute__ ((interrupt_handler)); // 38 TRAPA (User Vector) void INT_TRAPA38(void) __attribute__ ((interrupt_handler)); // 39 TRAPA (User Vector) void INT_TRAPA39(void) __attribute__ ((interrupt_handler)); // 40 TRAPA (User Vector) void INT_TRAPA40(void) __attribute__ ((interrupt_handler)); // 41 TRAPA (User Vector) void INT_TRAPA41(void) __attribute__ ((interrupt_handler)); // 42 TRAPA (User Vector) void INT_TRAPA42(void) __attribute__ ((interrupt_handler)); // 43 TRAPA (User Vector) void INT_TRAPA43(void) __attribute__ ((interrupt_handler)); // 44 TRAPA (User Vector) void INT_TRAPA44(void) __attribute__ ((interrupt_handler)); // 45 TRAPA (User Vector) void INT_TRAPA45(void) __attribute__ ((interrupt_handler)); // 46 TRAPA (User Vector) void INT_TRAPA46(void) __attribute__ ((interrupt_handler)); // 47 TRAPA (User Vector) void INT_TRAPA47(void) __attribute__ ((interrupt_handler)); // 48 TRAPA (User Vector) void INT_TRAPA48(void) __attribute__ ((interrupt_handler)); // 49 TRAPA (User Vector) void INT_TRAPA49(void) __attribute__ ((interrupt_handler)); // 50 TRAPA (User Vector) void INT_TRAPA50(void) __attribute__ ((interrupt_handler)); // 51 TRAPA (User Vector) void INT_TRAPA51(void) __attribute__ ((interrupt_handler)); // 52 TRAPA (User Vector) void INT_TRAPA52(void) __attribute__ ((interrupt_handler)); // 53 TRAPA (User Vector) void INT_TRAPA53(void) __attribute__ ((interrupt_handler)); // 54 TRAPA (User Vector) void INT_TRAPA54(void) __attribute__ ((interrupt_handler)); // 55 TRAPA (User Vector) void INT_TRAPA55(void) __attribute__ ((interrupt_handler)); // 56 TRAPA (User Vector) void INT_TRAPA56(void) __attribute__ ((interrupt_handler)); // 57 TRAPA (User Vector) void INT_TRAPA57(void) __attribute__ ((interrupt_handler)); // 58 TRAPA (User Vector) void INT_TRAPA58(void) __attribute__ ((interrupt_handler)); // 59 TRAPA (User Vector) void INT_TRAPA59(void) __attribute__ ((interrupt_handler)); // 60 TRAPA (User Vector) void INT_TRAPA60(void) __attribute__ ((interrupt_handler)); // 61 TRAPA (User Vector) void INT_TRAPA61(void) __attribute__ ((interrupt_handler)); // 62 TRAPA (User Vector) void INT_TRAPA62(void) __attribute__ ((interrupt_handler)); // 63 TRAPA (User Vector) void INT_TRAPA63(void) __attribute__ ((interrupt_handler)); // 64 Interrupt IRQ0 void INT_IRQ0(void) __attribute__ ((interrupt_handler)); // 65 Interrupt IRQ1 void INT_IRQ1(void) __attribute__ ((interrupt_handler)); // 66 Interrupt IRQ2 void INT_IRQ2(void) __attribute__ ((interrupt_handler)); // 67 Interrupt IRQ3 void INT_IRQ3(void) __attribute__ ((interrupt_handler)); // 68 Interrupt IRQ4 void INT_IRQ4(void) __attribute__ ((interrupt_handler)); // 69 Interrupt IRQ5 void INT_IRQ5(void) __attribute__ ((interrupt_handler)); // 70 Interrupt IRQ6 void INT_IRQ6(void) __attribute__ ((interrupt_handler)); // 71 Interrupt IRQ7 void INT_IRQ7(void) __attribute__ ((interrupt_handler)); // 72 Reserved // 73 Reserved // 74 Reserved // 75 Reserved // 76 Reserved // 77 Reserved // 78 Reserved // 79 Reserved // 80 Reserved // 81 Reserved // 82 Reserved // 83 Reserved // 84 Reserved // 85 Reserved // 86 Reserved // 87 Reserved // 88 Reserved // 89 Reserved // 90 Reserved // 91 ROMFLD FIFE void INT_ROMFLD_FIFE(void) __attribute__ ((interrupt_handler)); // 92 ADC ADI0 void INT_ADC_ADI0(void) __attribute__ ((interrupt_handler)); // 93 Reserved // 94 Reserved // 95 Reserved // 96 ADC ADI1 void INT_ADC_ADI1(void) __attribute__ ((interrupt_handler)); // 97 Reserved // 98 Reserved // 99 Reserved // 100 Reserved // 101 Reserved // 102 Reserved // 103 Reserved // 104 RCAN ERS0 void INT_RCAN_ERS0(void) __attribute__ ((interrupt_handler)); // 105 RCAN OVR0 void INT_RCAN_OVR0(void) __attribute__ ((interrupt_handler)); // 106 RCAN RM00 RM10 void INT_RCAN_RM00_RM10(void) __attribute__ ((interrupt_handler)); // 107 RCAN SLE0 void INT_SLE0(void) __attribute__ ((interrupt_handler)); // 108 DMAC0 DEI void INT_DMAC0_DEI0(void) __attribute__ ((interrupt_handler)); // 109 DMAC0 HEI void INT_DMAC0_HEI0(void) __attribute__ ((interrupt_handler)); // 110 Reserved // 111 Reserved // 112 DMAC1 DEI void INT_DMAC1_DEI1(void) __attribute__ ((interrupt_handler)); // 113 DMAC1 HEI void INT_DMAC1_HEI1(void) __attribute__ ((interrupt_handler)); // 114 Reserved // 115 Reserved // 116 DMAC2 DEI void INT_DMAC2_DEI2(void) __attribute__ ((interrupt_handler)); // 117 DMAC2 HEI void INT_DMAC2_HEI2(void) __attribute__ ((interrupt_handler)); // 118 Reserved // 119 Reserved // 120 DMAC3 DEI void INT_DMAC3_DEI3(void) __attribute__ ((interrupt_handler)); // 121 DMAC3 HEI void INT_DMAC3_HEI3(void) __attribute__ ((interrupt_handler)); // 122 Reserved // 123 Reserved // 124 DMAC4 DEI void INT_DMAC4_DEI4(void) __attribute__ ((interrupt_handler)); // 125 DMAC4 HEI void INT_DMAC4_HEI4(void) __attribute__ ((interrupt_handler)); // 126 Reserved // 127 Reserved // 128 DMAC5 DEI void INT_DMAC5_DEI5(void) __attribute__ ((interrupt_handler)); // 129 DMAC5 HEI void INT_DMAC5_HEI5(void) __attribute__ ((interrupt_handler)); // 130 Reserved // 131 Reserved // 132 DMAC6 DEI void INT_DMAC6_DEI6(void) __attribute__ ((interrupt_handler)); // 133 DMAC6 HEI void INT_DMAC6_HEI6(void) __attribute__ ((interrupt_handler)); // 134 Reserved // 135 Reserved // 136 DMAC7 DEI void INT_DMAC7_DEI7(void) __attribute__ ((interrupt_handler)); // 137 DMAC7 HEI void INT_DMAC7_HEI7(void) __attribute__ ((interrupt_handler)); // 138 Reserved // 139 Reserved // 140 CMT CMI0 void INT_CMT_CMI0(void) __attribute__ ((interrupt_handler)); // 141 Reserved // 142 Reserved // 143 Reserved // 144 CMT CMI1 void INT_CMT_CMI1(void) __attribute__ ((interrupt_handler)); // 145 Reserved // 146 Reserved // 147 Reserved // 148 BSC CMI void INT_BSC_CMI(void) __attribute__ ((interrupt_handler)); // 149 Reserved // 150 USB USBRXI1 void INT_USB_USBRXI1(void) __attribute__ ((interrupt_handler)); // 151 USB USBTXI1 void INT_USB_USBTXI1(void) __attribute__ ((interrupt_handler)); // 152 WDT ITI void INT_WDT_ITI(void) __attribute__ ((interrupt_handler)); // 153 ETHERC EINT0 void INT_ETHERC_EINT0(void) __attribute__ ((interrupt_handler)); // 154 USB USBRXI0 void INT_USB_USBRXI0(void) __attribute__ ((interrupt_handler)); // 155 USB USBTXI0 void INT_USB_USBTXI0(void) __attribute__ ((interrupt_handler)); // 156 MTU20 TGIA0 void INT_MTU20_TGIA0(void) __attribute__ ((interrupt_handler)); // 157 MTU20 TGIB0 void INT_MTU20_TGIB0(void) __attribute__ ((interrupt_handler)); // 158 MTU20 TGIC0 void INT_MTU20_TGIC0(void) __attribute__ ((interrupt_handler)); // 159 MTU20 TGID0 void INT_MTU20_TGID0(void) __attribute__ ((interrupt_handler)); // 160 MTU20 TCIV0 void INT_MTU20_TCIV0(void) __attribute__ ((interrupt_handler)); // 161 MTU20 TGIE0 void INT_MTU20_TGIE0(void) __attribute__ ((interrupt_handler)); // 162 MTU20 TGIF0 void INT_MTU20_TGIF0(void) __attribute__ ((interrupt_handler)); // 163 Reserved // 164 MTU21 TGIA1 void INT_MTU21_TGIA1(void) __attribute__ ((interrupt_handler)); // 165 MTU21 TGIB1 void INT_MTU21_TGIB1(void) __attribute__ ((interrupt_handler)); // 166 Reserved // 167 Reserved // 168 MTU21 TCIV1 void INT_MTU21_TCIV1(void) __attribute__ ((interrupt_handler)); // 169 MTU21 TCIU1 void INT_MTU21_TCIU1(void) __attribute__ ((interrupt_handler)); // 170 Reserved // 171 Reserved // 172 MTU22 TGIA2 void INT_MTU22_TGIA2(void) __attribute__ ((interrupt_handler)); // 173 MTU22 TGIB2 void INT_MTU22_TGIB2(void) __attribute__ ((interrupt_handler)); // 174 Reserved // 175 Reserved // 176 MTU22 TCIV2 void INT_MTU22_TCIV2(void) __attribute__ ((interrupt_handler)); // 177 MTU22 TCIU2 void INT_MTU22_TCIU2(void) __attribute__ ((interrupt_handler)); // 178 Reserved // 179 Reserved // 180 MTU23 TGIA3 void INT_MTU23_TGIA3(void) __attribute__ ((interrupt_handler)); // 181 MTU23 TGIB3 void INT_MTU23_TGIB3(void) __attribute__ ((interrupt_handler)); // 182 MTU23 TGIC3 void INT_MTU23_TGIC3(void) __attribute__ ((interrupt_handler)); // 183 MTU23 TGID3 void INT_MTU23_TGID3(void) __attribute__ ((interrupt_handler)); // 184 MTU23 TCIV3 void INT_MTU23_TCIV3(void) __attribute__ ((interrupt_handler)); // 185 Reserved // 186 Reserved // 187 Reserved // 188 MTU24 TGIA4 void INT_MTU24_TGIA4(void) __attribute__ ((interrupt_handler)); // 189 MTU24 TGIB4 void INT_MTU24_TGIB4(void) __attribute__ ((interrupt_handler)); // 190 MTU24 TGIC4 void INT_MTU24_TGIC4(void) __attribute__ ((interrupt_handler)); // 191 MTU24 TGID4 void INT_MTU24_TGID4(void) __attribute__ ((interrupt_handler)); // 192 MTU24 TCIV4 void INT_MTU24_TCIV4(void) __attribute__ ((interrupt_handler)); // 193 Reserved // 194 Reserved // 195 Reserved // 196 MTU25 TGIU5 void INT_MTU25_TGIU5(void) __attribute__ ((interrupt_handler)); // 197 MTU25 TGIV5 void INT_MTU25_TGIV5(void) __attribute__ ((interrupt_handler)); // 198 MTU25 TGIW5 void INT_MTU25_TGIW5(void) __attribute__ ((interrupt_handler)); // 199 Reserved // 200 POE2 OEI1 void INT_POE2_OEI1(void) __attribute__ ((interrupt_handler)); // 201 POE2 OEI2 void INT_POE2_OEI2(void) __attribute__ ((interrupt_handler)); // 202 Reserved // 203 Reserved // 204 MTU2S3 TGIA3S void INT_MTU2S3_TGIA3S(void) __attribute__ ((interrupt_handler)); // 205 MTU2S3 TGIB3S void INT_MTU2S3_TGIB3S(void) __attribute__ ((interrupt_handler)); // 206 MTU2S3 TGIC3S void INT_MTU2S3_TGIC3S(void) __attribute__ ((interrupt_handler)); // 207 MTU2S3 TGID3S void INT_MTU2S3_TGID3S(void) __attribute__ ((interrupt_handler)); // 208 MTU2S3 TCIV3S void INT_MTU2S3_TCIV3S(void) __attribute__ ((interrupt_handler)); // 209 Reserved // 210 Reserved // 211 Reserved // 212 MTU2S4 TGIA4S void INT_MTU2S4_TGIA4S(void) __attribute__ ((interrupt_handler)); // 213 MTU2S4 TGIB4S void INT_MTU2S4_TGIB4S(void) __attribute__ ((interrupt_handler)); // 214 MTU2S4 TGIC4S void INT_MTU2S4_TGIC4S(void) __attribute__ ((interrupt_handler)); // 215 MTU2S4 TGID4S void INT_MTU2S4_TGID4S(void) __attribute__ ((interrupt_handler)); // 216 MTU2S4 TCIV4S void INT_MTU2S4_TCIV4S(void) __attribute__ ((interrupt_handler)); // 217 Reserved // 218 Reserved // 219 Reserved // 220 MTU2S5 TGIU5S void INT_MTU2S5_TGIU5S(void) __attribute__ ((interrupt_handler)); // 221 MTU2S5 TGIV5S void INT_MTU2S5_TGIV5S(void) __attribute__ ((interrupt_handler)); // 222 MTU2S5 TGIW5S void INT_MTU2S5_TGIW5S(void) __attribute__ ((interrupt_handler)); // 223 Reserved // 224 POE2 OEI3 void INT_POE2_OEI3(void) __attribute__ ((interrupt_handler)); // 225 Reserved // 226 USB USI0 void INT_USB_USI0(void) __attribute__ ((interrupt_handler)); // 227 USB USI1 void INT_USB_USI1(void) __attribute__ ((interrupt_handler)); // 228 IIC3 STPI void INT_IIC3_STPI(void) __attribute__ ((interrupt_handler)); // 229 IIC3 NAKI void INT_IIC3_NAKI(void) __attribute__ ((interrupt_handler)); // 230 IIC3 RXI void INT_IIC3_RXI(void) __attribute__ ((interrupt_handler)); // 231 IIC3 TXI void INT_IIC3_TXI(void) __attribute__ ((interrupt_handler)); // 232 IIC3 TEI void INT_IIC3_TEI(void) __attribute__ ((interrupt_handler)); // 233 RSPI SPEI void INT_RSPI_SPEI(void) __attribute__ ((interrupt_handler)); // 234 RSPI SPRI void INT_RSPI_SPRI(void) __attribute__ ((interrupt_handler)); // 235 RSPI SPTI void INT_RSPI_SPTI(void) __attribute__ ((interrupt_handler)); // 236 SCI SCI4 ERI4 void INT_SCI_SCI4_ERI4(void) __attribute__ ((interrupt_handler)); // 237 SCI SCI4 RXI4 void INT_SCI_SCI4_RXI4(void) __attribute__ ((interrupt_handler)); // 238 SCI SCI4 TXI4 void INT_SCI_SCI4_TXI4(void) __attribute__ ((interrupt_handler)); // 239 SCI SCI4 TEI4 void INT_SCI_SCI4_TEI4(void) __attribute__ ((interrupt_handler)); // 240 SCI SCI0 ERI0 void INT_SCI_SCI0_ERI0(void) __attribute__ ((interrupt_handler)); // 241 SCI SCI0 RXI0 void INT_SCI_SCI0_RXI0(void) __attribute__ ((interrupt_handler)); // 242 SCI SCI0 TXI0 void INT_SCI_SCI0_TXI0(void) __attribute__ ((interrupt_handler)); // 243 SCI SCI0 TEI0 void INT_SCI_SCI0_TEI0(void) __attribute__ ((interrupt_handler)); // 244 SCI SCI1 ERI1 void INT_SCI_SCI1_ERI1(void) __attribute__ ((interrupt_handler)); // 245 SCI SCI1 RXI1 void INT_SCI_SCI1_RXI1(void) __attribute__ ((interrupt_handler)); // 246 SCI SCI1 TXI1 void INT_SCI_SCI1_TXI1(void) __attribute__ ((interrupt_handler)); // 247 SCI SCI1 TEI1 void INT_SCI_SCI1_TEI1(void) __attribute__ ((interrupt_handler)); // 248 SCI SCI2 ERI2 void INT_SCI_SCI2_ERI2(void) __attribute__ ((interrupt_handler)); // 249 SCI SCI2 RXI2 void INT_SCI_SCI2_RXI2(void) __attribute__ ((interrupt_handler)); // 250 SCI SCI2 TXI2 void INT_SCI_SCI2_TXI2(void) __attribute__ ((interrupt_handler)); // 251 SCI SCI2 TEI2 void INT_SCI_SCI2_TEI2(void) __attribute__ ((interrupt_handler)); // 252 SCIF SCIF3 BRI3 void INT_SCIF_SCIF3_BRI3(void) __attribute__ ((interrupt_handler)); // 253 SCIF SCIF3 ERI3 void INT_SCIF_SCIF3_ERI3(void) __attribute__ ((interrupt_handler)); // 254 SCIF SCIF3 RXI3 void INT_SCIF_SCIF3_RXI3(void) __attribute__ ((interrupt_handler)); // 255 SCIF SCIF3 TXI3 void INT_SCIF_SCIF3_TXI3(void) __attribute__ ((interrupt_handler)); // Dummy void INT_Dummy(void) __attribute__ ((interrupt_handler)); #endif /* VECT_H */ /* End of File */

VECTTBL￥SH7216.c ベクターテーブル（文字がない部分もコピーして張り付ける）

　　 /********************************************************************* * * Device : SH2A-FPU/SH7216 * * File Name : vecttbl.c * * Abstract : Initialize of Vector Table. * * History : 1.00 (2009-04-28) [Hardware Manual Revision : 1.01] * * NOTE : THIS IS A TYPICAL EXAMPLE. * * Copyright(c) 2008 Renesas Technology Corp. * And Renesas Solutions Corp.,All Rights Reserved. * *********************************************************************/ #include "inthandler.h" typedef void (*fp) (void); extern void start(void); /* Startup code (in start.s) */ extern void stack (void); #define VECT_SECT __attribute__ ((section (".vects"))) const fp HardwareVectors[] VECT_SECT = { //;<<VECTOR DATA START (POWER ON RESET)>> //;0 Power On Reset PC start, //;<<VECTOR DATA END (POWER ON RESET)>> // 1 Power On Reset SP (fp)stack, //;<<VECTOR DATA START (MANUAL RESET)>> //;2 Manual Reset PC Manual_Reset_PC, //;<<VECTOR DATA END (MANUAL RESET)>> // 3 Manual Reset SP (fp)stack, // 4 Illegal code INT_Illegal_code, // 5 Reserved INT_Dummy, // 6 Illegal slot INT_Illegal_slot, // 7 Reserved INT_Dummy, // 8 Reserved INT_Dummy, // 9 CPU Address error INT_CPU_Address, // 10 DMAC Address erro INT_DMAC_Address, // 11 NMI INT_NMI, // 12 User breakpoint trap INT_User_Break, // 13 INT_FPU INT_FPU, // 14 H-UDI INT_HUDI, // 15 Bank Overflow INT_Bank_Overflow, // 16 Bank Underflow INT_Bank_Underflow, // 17 Divide by zero INT_Divide_by_Zero, // 18 Divide Overflow INT_Divide_Overflow, // 19 Reserved INT_Dummy, // 20 Reserved INT_Dummy, // 21 Reserved INT_Dummy, // 22 Reserved INT_Dummy, // 23 Reserved INT_Dummy, // 24 Reserved INT_Dummy, // 25 Reserved INT_Dummy, // 26 Reserved INT_Dummy, // 27 Reserved INT_Dummy, // 28 Reserved INT_Dummy, // 29 Reserved INT_Dummy, // 30 Reserved INT_Dummy, // 31 Reserved INT_Dummy, // 32 TRAPA (User Vector) INT_TRAPA32, // 33 TRAPA (User Vector) INT_TRAPA33, // 34 TRAPA (User Vector) INT_TRAPA34, // 35 TRAPA (User Vector) INT_TRAPA35, // 36 TRAPA (User Vector) INT_TRAPA36, // 37 TRAPA (User Vector) INT_TRAPA37, // 38 TRAPA (User Vector) INT_TRAPA38, // 39 TRAPA (User Vector) INT_TRAPA39, // 40 TRAPA (User Vector) INT_TRAPA40, // 41 TRAPA (User Vector) INT_TRAPA41, // 42 TRAPA (User Vector) INT_TRAPA42, // 43 TRAPA (User Vector) INT_TRAPA43, // 44 TRAPA (User Vector) INT_TRAPA44, // 45 TRAPA (User Vector) INT_TRAPA45, // 46 TRAPA (User Vector) INT_TRAPA46, // 47 TRAPA (User Vector) INT_TRAPA47, // 48 TRAPA (User Vector) INT_TRAPA48, // 49 TRAPA (User Vector) INT_TRAPA49, // 50 TRAPA (User Vector) INT_TRAPA50, // 51 TRAPA (User Vector) INT_TRAPA51, // 52 TRAPA (User Vector) INT_TRAPA52, // 53 TRAPA (User Vector) INT_TRAPA53, // 54 TRAPA (User Vector) INT_TRAPA54, // 55 TRAPA (User Vector) INT_TRAPA55, // 56 TRAPA (User Vector) INT_TRAPA56, // 57 TRAPA (User Vector) INT_TRAPA57, // 58 TRAPA (User Vector) INT_TRAPA58, // 59 TRAPA (User Vector) INT_TRAPA59, // 60 TRAPA (User Vector) INT_TRAPA60, // 61 TRAPA (User Vector) INT_TRAPA61, // 62 TRAPA (User Vector) INT_TRAPA62, // 63 TRAPA (User Vector) INT_TRAPA63, // 64 Interrupt IRQ0 INT_IRQ0, // 65 Interrupt IRQ1 INT_IRQ1, // 66 Interrupt IRQ2 INT_IRQ2, // 67 Interrupt IRQ3 INT_IRQ3, // 68 Interrupt IRQ4 INT_IRQ4, // 69 Interrupt IRQ5 INT_IRQ5, // 70 Interrupt IRQ6 INT_IRQ6, // 71 Interrupt IRQ7 INT_IRQ7, // 72 Reserved INT_Dummy, // 73 Reserved INT_Dummy, // 74 Reserved INT_Dummy, // 75 Reserved INT_Dummy, // 76 Reserved INT_Dummy, // 77 Reserved INT_Dummy, // 78 Reserved INT_Dummy, // 79 Reserved INT_Dummy, // 80 Reserved INT_Dummy, // 81 Reserved INT_Dummy, // 82 Reserved INT_Dummy, // 83 Reserved INT_Dummy, // 84 Reserved INT_Dummy, // 85 Reserved INT_Dummy, // 86 Reserved INT_Dummy, // 87 Reserved INT_Dummy, // 88 Reserved INT_Dummy, // 89 Reserved INT_Dummy, // 90 Reserved INT_Dummy, // 91 ROMFLD FIFE INT_ROMFLD_FIFE, // 92 ADC ADI0 INT_ADC_ADI0, // 93 Reserved INT_Dummy, // 94 Reserved INT_Dummy, // 95 Reserved INT_Dummy, // 96 ADC ADI1 INT_ADC_ADI1, // 97 Reserved INT_Dummy, // 98 Reserved INT_Dummy, // 99 Reserved INT_Dummy, // 100 Reserved INT_Dummy, // 101 Reserved INT_Dummy, // 102 Reserved INT_Dummy, // 103 Reserved INT_Dummy, // 104 RCAN ERS0 INT_RCAN_ERS0, // 105 RCAN OVR0 INT_RCAN_OVR0, // 106 RCAN RM00 RM10 INT_RCAN_RM00_RM10, // 107 RCAN SLE0 INT_SLE0, // 108 DMAC0 DEI INT_DMAC0_DEI0, // 109 DMAC0 HEI INT_DMAC0_HEI0, // 110 Reserved INT_Dummy, // 111 Reserved INT_Dummy, // 112 DMAC1 DEI INT_DMAC1_DEI1, // 113 DMAC1 HEI INT_DMAC1_HEI1, // 114 Reserved INT_Dummy, // 115 Reserved INT_Dummy, // 116 DMAC2 DEI INT_DMAC2_DEI2, // 117 DMAC2 HEI INT_DMAC2_HEI2, // 118 Reserved INT_Dummy, // 119 Reserved INT_Dummy, // 120 DMAC3 DEI INT_DMAC3_DEI3, // 121 DMAC3 HEI INT_DMAC3_HEI3, // 122 Reserved INT_Dummy, // 123 Reserved INT_Dummy, // 124 DMAC4 DEI INT_DMAC4_DEI4, // 125 DMAC4 HEI INT_DMAC4_HEI4, // 126 Reserved INT_Dummy, // 127 Reserved INT_Dummy, // 128 DMAC5 DEI INT_DMAC5_DEI5, // 129 DMAC5 HEI INT_DMAC5_HEI5, // 130 Reserved INT_Dummy, // 131 Reserved INT_Dummy, // 132 DMAC6 DEI INT_DMAC6_DEI6, // 133 DMAC6 HEI INT_DMAC6_HEI6, // 134 Reserved INT_Dummy, // 135 Reserved INT_Dummy, // 136 DMAC7 DEI INT_DMAC7_DEI7, // 137 DMAC7 HEI INT_DMAC7_HEI7, // 138 Reserved INT_Dummy, // 139 Reserved INT_Dummy, // 140 CMT CMI0 INT_CMT_CMI0, // 141 Reserved INT_Dummy, // 142 Reserved INT_Dummy, // 143 Reserved INT_Dummy, // 144 CMT CMI1 INT_CMT_CMI1, // 145 Reserved INT_Dummy, // 146 Reserved INT_Dummy, // 147 Reserved INT_Dummy, // 148 BSC CMI INT_BSC_CMI, // 149 Reserved INT_Dummy, // 150 USB USBRXI1 INT_USB_USBRXI1, // 151 USB USBTXI1 INT_USB_USBTXI1, // 152 WDT ITI INT_WDT_ITI, // 153 ETHERC EINT0 INT_ETHERC_EINT0, // 154 USB USBRXI0 INT_USB_USBRXI0, // 155 USB USBTXI0 INT_USB_USBTXI0, // 156 MTU20 TGIA0 INT_MTU20_TGIA0, // 157 MTU20 TGIB0 INT_MTU20_TGIB0, // 158 MTU20 TGIC0 INT_MTU20_TGIC0, // 159 MTU20 TGID0 INT_MTU20_TGID0, // 160 MTU20 TCIV0 INT_MTU20_TCIV0, // 161 MTU20 TGIE0 INT_MTU20_TGIE0, // 162 MTU20 TGIF0 INT_MTU20_TGIF0, // 163 Reserved INT_Dummy, // 164 MTU21 TGIA1 INT_MTU21_TGIA1, // 165 MTU21 TGIB1 INT_MTU21_TGIB1, // 166 Reserved INT_Dummy, // 167 Reserved INT_Dummy, // 168 MTU21 TCIV1 INT_MTU21_TCIV1, // 169 MTU21 TCIU1 INT_MTU21_TCIU1, // 170 Reserved INT_Dummy, // 171 Reserved INT_Dummy, // 172 MTU22 TGIA2 INT_MTU22_TGIA2, // 173 MTU22 TGIB2 INT_MTU22_TGIB2, // 174 Reserved INT_Dummy, // 175 Reserved INT_Dummy, // 176 MTU22 TCIV2 INT_MTU22_TCIV2, // 177 MTU22 TCIU2 INT_MTU22_TCIU2, // 178 Reserved INT_Dummy, // 179 Reserved INT_Dummy, // 180 MTU23 TGIA3 INT_MTU23_TGIA3, // 181 MTU23 TGIB3 INT_MTU23_TGIB3, // 182 MTU23 TGIC3 INT_MTU23_TGIC3, // 183 MTU23 TGID3 INT_MTU23_TGID3, // 184 MTU23 TCIV3 INT_MTU23_TCIV3, // 185 Reserved INT_Dummy, // 186 Reserved INT_Dummy, // 187 Reserved INT_Dummy, // 188 MTU24 TGIA4 INT_MTU24_TGIA4, // 189 MTU24 TGIB4 INT_MTU24_TGIB4, // 190 MTU24 TGIC4 INT_MTU24_TGIC4, // 191 MTU24 TGID4 INT_MTU24_TGID4, // 192 MTU24 TCIV4 INT_MTU24_TCIV4, // 193 Reserved INT_Dummy, // 194 Reserved INT_Dummy, // 195 Reserved INT_Dummy, // 196 MTU25 TGIU5 INT_MTU25_TGIU5, // 197 MTU25 TGIV5 INT_MTU25_TGIV5, // 198 MTU25 TGIW5 INT_MTU25_TGIW5, // 199 Reserved INT_Dummy, // 200 POE2 OEI1 INT_POE2_OEI1, // 201 POE2 OEI2 INT_POE2_OEI2, // 202 Reserved INT_Dummy, // 203 Reserved INT_Dummy, // 204 MTU2S3 TGIA3S INT_MTU2S3_TGIA3S, // 205 MTU2S3 TGIB3S INT_MTU2S3_TGIB3S, // 206 MTU2S3 TGIC3S INT_MTU2S3_TGIC3S, // 207 MTU2S3 TGID3S INT_MTU2S3_TGID3S, // 208 MTU2S3 TCIV3S INT_MTU2S3_TCIV3S, // 209 Reserved INT_Dummy, // 210 Reserved INT_Dummy, // 211 Reserved INT_Dummy, // 212 MTU2S4 TGIA4S INT_MTU2S4_TGIA4S, // 213 MTU2S4 TGIB4S INT_MTU2S4_TGIB4S, // 214 MTU2S4 TGIC4S INT_MTU2S4_TGIC4S, // 215 MTU2S4 TGID4S INT_MTU2S4_TGID4S, // 216 MTU2S4 TCIV4S INT_MTU2S4_TCIV4S, // 217 Reserved INT_Dummy, // 218 Reserved INT_Dummy, // 219 Reserved INT_Dummy, // 220 MTU2S5 TGIU5S INT_MTU2S5_TGIU5S, // 221 MTU2S5 TGIV5S INT_MTU2S5_TGIV5S, // 222 MTU2S5 TGIW5S INT_MTU2S5_TGIW5S, // 223 Reserved INT_Dummy, // 224 POE2 OEI3 INT_POE2_OEI3, // 225 Reserved INT_Dummy, // 226 USB USI0 INT_USB_USI0, // 227 USB USI1 INT_USB_USI1, // 228 IIC3 STPI INT_IIC3_STPI, // 229 IIC3 NAKI INT_IIC3_NAKI, // 230 IIC3 RXI INT_IIC3_RXI, // 231 IIC3 TXI INT_IIC3_TXI, // 232 IIC3 TEI INT_IIC3_TEI, // 233 RSPI SPEI INT_RSPI_SPEI, // 234 RSPI SPRI INT_RSPI_SPRI, // 235 RSPI SPTI INT_RSPI_SPTI, // 236 SCI SCI4 ERI4 INT_SCI_SCI4_ERI4, // 237 SCI SCI4 RXI4 INT_SCI_SCI4_RXI4, // 238 SCI SCI4 TXI4 INT_SCI_SCI4_TXI4, // 239 SCI SCI4 TEI4 INT_SCI_SCI4_TEI4, // 240 SCI SCI0 ERI0 INT_SCI_SCI0_ERI0, // 241 SCI SCI0 RXI0 INT_SCI_SCI0_RXI0, // 242 SCI SCI0 TXI0 INT_SCI_SCI0_TXI0, // 243 SCI SCI0 TEI0 INT_SCI_SCI0_TEI0, // 244 SCI SCI1 ERI1 INT_SCI_SCI1_ERI1, // 245 SCI SCI1 RXI1 INT_SCI_SCI1_RXI1, // 246 SCI SCI1 TXI1 INT_SCI_SCI1_TXI1, // 247 SCI SCI1 TEI1 INT_SCI_SCI1_TEI1, // 248 SCI SCI2 ERI2 INT_SCI_SCI2_ERI2, // 249 SCI SCI2 RXI2 INT_SCI_SCI2_RXI2, // 250 SCI SCI2 TXI2 INT_SCI_SCI2_TXI2, // 251 SCI SCI2 TEI2 INT_SCI_SCI2_TEI2, // 252 SCIF SCIF3 BRI3 INT_SCIF_SCIF3_BRI3, // 253 SCIF SCIF3 ERI3 INT_SCIF_SCIF3_ERI3, // 254 SCIF SCIF3 RXI3 INT_SCIF_SCIF3_RXI3, // 255 SCIF SCIF3 TXI3 INT_SCIF_SCIF3_TXI3, };

Hardware￥SH-2A￥SH7216.dat ハードウェア情報

　　[Version] Version=1.0 [Mode] DEFAULT_MODE=05 MODE=01_05,03_07,04_07,05_07 [Memory MAP] MAP_01_00=0x00000000,0x1FFFFFFF,EXT,32,0101 MAP_01_01=0xF0000000,0xF5FFFFFF,I/O,32,0101 MAP_01_02=0xFFF80000,0xFFF9FFFF,RAM,32,0101 MAP_01_03=0xFFFC0000,0xFFFCFFFF,I/O,32,0101 MAP_01_04=0xFFFD0000,0xFFFFFFFF,I/O,16,0101 MAP_03_00=0x00000000,0x0007FFFF,ROM,32,0202 MAP_03_01=0x80100000,0x80107FFF,ROM,16,0101 MAP_03_02=0x80FF8000,0x80FF9FFF,RAM,32,0101 MAP_03_03=0xF0000000,0xF5FFFFFF,I/O,32,0101 MAP_03_04=0xFFF80000,0xFFF8FFFF,RAM,32,0101 MAP_03_05=0xFFFC0000,0xFFFCFFFF,I/O,32,0101 MAP_03_06=0xFFFD0000,0xFFFFFFFF,I/O,16,0101 MAP_04_00=0x00000000,0x000BFFFF,ROM,32,0202 MAP_04_01=0x80100000,0x80107FFF,ROM,16,0101 MAP_04_02=0x80FF8000,0x80FF9FFF,RAM,32,0101 MAP_04_03=0xF0000000,0xF5FFFFFF,I/O,32,0101 MAP_04_04=0xFFF80000,0xFFF97FFF,RAM,32,0101 MAP_04_05=0xFFFC0000,0xFFFCFFFF,I/O,32,0101 MAP_04_06=0xFFFD0000,0xFFFFFFFF,I/O,16,0101 MAP_05_00=0x00000000,0x000FFFFF,ROM,32,0202 MAP_05_01=0x80100000,0x80107FFF,ROM,16,0101 MAP_05_02=0x80FF8000,0x80FF9FFF,RAM,32,0101 MAP_05_03=0xF0000000,0xF5FFFFFF,I/O,32,0101 MAP_05_04=0xFFF80000,0xFFF9FFFF,RAM,32,0101 MAP_05_05=0xFFFC0000,0xFFFCFFFF,I/O,32,0101 MAP_05_06=0xFFFD0000,0xFFFFFFFF,I/O,16,0101 [Simulator] ROM_MODE=ROM Disable|01,ROM Enable/512K byte|03,ROM Enable/768K byte|04,ROM Enable/1M byte|05 RESOURCE_01=0x00000000,0x0000FFFF,R/W 0xFFF80000,0xFFF9FFFF,R/W 0xFFFC0000,0xFFFCFFFF,R/W 0xFFFD0000,0xFFFFFFFF,R/W RESOURCE_03=0x00000000,0x0007FFFF,R 0xFFF80000,0xFFF8FFFF,R/W 0xFFFC0000,0xFFFCFFFF,R/W 0xFFFD0000,0xFFFFFFFF,R/W RESOURCE_04=0x00000000,0x000BFFFF,R 0xFFF80000,0xFFF97FFF,R/W 0xFFFC0000,0xFFFCFFFF,R/W 0xFFFD0000,0xFFFFFFFF,R/W RESOURCE_05=0x00000000,0x000FFFFF,R 0xFFF80000,0xFFF9FFFF,R/W 0xFFFC0000,0xFFFCFFFF,R/W 0xFFFD0000,0xFFFFFFFF,R/W SIMIOADR=0x0

FPU 付が SH-2A で FPU なしが SH2A-NoFPU となっている。
Renesas の場合は
FPU 付が SH2A-FPU で FPU なしが SH2A となっている。
紛らわしいのでそのうち整理しよう。

環境： (HEW Version 4.07.01.004) + (KPIT GNUSH v1001 Windows Tool Chain (ELF))

コメントをどうぞ

※メールアドレスとURLの入力は必須ではありません。入力されたメールアドレスは記事に反映されず、ブログの管理者のみが参照できます。

※投稿には管理者が設定した質問に答える必要があります。

トラックバック

このエントリのトラックバックURL: http://syslab.asablo.jp/blog/2010/04/23/5040262/tb

<<前次>>

SYSLAB blog

このブログについて

カテゴリ一覧

最近のコメント

最近のトラックバック

バックナンバー

メモ

検索

LOVE in Action

携帯からアクセス

RSS

KPIT GNU Tools (14) GNUSH v1001 Windows Tool Chain (ELF) ― 2010年04月23日 23時23分35秒

コメント

トラックバック

<< 2010/04 >>
日	月	火	水	木	金	土
				01	02	03
04	05	06	07	08	09	10
11	12	13	14	15	16	17
18	19	20	21	22	23	24
25	26	27	28	29	30

SYSLAB blog

このブログについて

カテゴリ一覧

最近のコメント

最近のトラックバック

バックナンバー

メモ

検索

LOVE in Action

携帯からアクセス

RSS

ログイン

KPIT GNU Tools (14) GNUSH v1001 Windows Tool Chain (ELF) ― 2010年04月23日 23時23分35秒

コメント

トラックバック